esp32c6/
soc_etm.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    ch_ena_ad0: CH_ENA_AD0,
6    ch_ena_ad0_set: CH_ENA_AD0_SET,
7    ch_ena_ad0_clr: CH_ENA_AD0_CLR,
8    ch_ena_ad1: CH_ENA_AD1,
9    ch_ena_ad1_set: CH_ENA_AD1_SET,
10    ch_ena_ad1_clr: CH_ENA_AD1_CLR,
11    ch: [CH; 50],
12    clk_en: CLK_EN,
13    date: DATE,
14}
15impl RegisterBlock {
16    #[doc = "0x00 - channel enable register"]
17    #[inline(always)]
18    pub const fn ch_ena_ad0(&self) -> &CH_ENA_AD0 {
19        &self.ch_ena_ad0
20    }
21    #[doc = "0x04 - channel enable set register"]
22    #[inline(always)]
23    pub const fn ch_ena_ad0_set(&self) -> &CH_ENA_AD0_SET {
24        &self.ch_ena_ad0_set
25    }
26    #[doc = "0x08 - channel enable clear register"]
27    #[inline(always)]
28    pub const fn ch_ena_ad0_clr(&self) -> &CH_ENA_AD0_CLR {
29        &self.ch_ena_ad0_clr
30    }
31    #[doc = "0x0c - channel enable register"]
32    #[inline(always)]
33    pub const fn ch_ena_ad1(&self) -> &CH_ENA_AD1 {
34        &self.ch_ena_ad1
35    }
36    #[doc = "0x10 - channel enable set register"]
37    #[inline(always)]
38    pub const fn ch_ena_ad1_set(&self) -> &CH_ENA_AD1_SET {
39        &self.ch_ena_ad1_set
40    }
41    #[doc = "0x14 - channel enable clear register"]
42    #[inline(always)]
43    pub const fn ch_ena_ad1_clr(&self) -> &CH_ENA_AD1_CLR {
44        &self.ch_ena_ad1_clr
45    }
46    #[doc = "0x18..0x1a8 - Cluster CH%s, containing CH*_EVT_ID, CH*_TASK_ID"]
47    #[inline(always)]
48    pub const fn ch(&self, n: usize) -> &CH {
49        &self.ch[n]
50    }
51    #[doc = "Iterator for array of:"]
52    #[doc = "0x18..0x1a8 - Cluster CH%s, containing CH*_EVT_ID, CH*_TASK_ID"]
53    #[inline(always)]
54    pub fn ch_iter(&self) -> impl Iterator<Item = &CH> {
55        self.ch.iter()
56    }
57    #[doc = "0x1a8 - etm clock enable register"]
58    #[inline(always)]
59    pub const fn clk_en(&self) -> &CLK_EN {
60        &self.clk_en
61    }
62    #[doc = "0x1ac - etm date register"]
63    #[inline(always)]
64    pub const fn date(&self) -> &DATE {
65        &self.date
66    }
67}
68#[doc = "CH_ENA_AD0 (rw) register accessor: channel enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ena_ad0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0`] module"]
69pub type CH_ENA_AD0 = crate::Reg<ch_ena_ad0::CH_ENA_AD0_SPEC>;
70#[doc = "channel enable register"]
71pub mod ch_ena_ad0;
72#[doc = "CH_ENA_AD0_SET (w) register accessor: channel enable set register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad0_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0_set`] module"]
73pub type CH_ENA_AD0_SET = crate::Reg<ch_ena_ad0_set::CH_ENA_AD0_SET_SPEC>;
74#[doc = "channel enable set register"]
75pub mod ch_ena_ad0_set;
76#[doc = "CH_ENA_AD0_CLR (w) register accessor: channel enable clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad0_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad0_clr`] module"]
77pub type CH_ENA_AD0_CLR = crate::Reg<ch_ena_ad0_clr::CH_ENA_AD0_CLR_SPEC>;
78#[doc = "channel enable clear register"]
79pub mod ch_ena_ad0_clr;
80#[doc = "CH_ENA_AD1 (rw) register accessor: channel enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_ena_ad1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1`] module"]
81pub type CH_ENA_AD1 = crate::Reg<ch_ena_ad1::CH_ENA_AD1_SPEC>;
82#[doc = "channel enable register"]
83pub mod ch_ena_ad1;
84#[doc = "CH_ENA_AD1_SET (w) register accessor: channel enable set register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad1_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1_set`] module"]
85pub type CH_ENA_AD1_SET = crate::Reg<ch_ena_ad1_set::CH_ENA_AD1_SET_SPEC>;
86#[doc = "channel enable set register"]
87pub mod ch_ena_ad1_set;
88#[doc = "CH_ENA_AD1_CLR (w) register accessor: channel enable clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_ena_ad1_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ch_ena_ad1_clr`] module"]
89pub type CH_ENA_AD1_CLR = crate::Reg<ch_ena_ad1_clr::CH_ENA_AD1_CLR_SPEC>;
90#[doc = "channel enable clear register"]
91pub mod ch_ena_ad1_clr;
92#[doc = "Cluster CH%s, containing CH*_EVT_ID, CH*_TASK_ID"]
93pub use self::ch::CH;
94#[doc = r"Cluster"]
95#[doc = "Cluster CH%s, containing CH*_EVT_ID, CH*_TASK_ID"]
96pub mod ch;
97#[doc = "CLK_EN (rw) register accessor: etm clock enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_en::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_en::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_en`] module"]
98pub type CLK_EN = crate::Reg<clk_en::CLK_EN_SPEC>;
99#[doc = "etm clock enable register"]
100pub mod clk_en;
101#[doc = "DATE (rw) register accessor: etm date register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
102pub type DATE = crate::Reg<date::DATE_SPEC>;
103#[doc = "etm date register"]
104pub mod date;