1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 slcconf0: SLCCONF0,
6 slc0int_raw: SLC0INT_RAW,
7 slc0int_st: SLC0INT_ST,
8 slc0int_ena: SLC0INT_ENA,
9 slc0int_clr: SLC0INT_CLR,
10 slc1int_raw: SLC1INT_RAW,
11 _reserved6: [u8; 0x08],
12 slc1int_clr: SLC1INT_CLR,
13 _reserved7: [u8; 0x18],
14 slc0rx_link: SLC0RX_LINK,
15 slc0rx_link_addr: SLC0RX_LINK_ADDR,
16 slc0tx_link: SLC0TX_LINK,
17 slc0tx_link_addr: SLC0TX_LINK_ADDR,
18 slc1rx_link: SLC1RX_LINK,
19 slc1rx_link_addr: SLC1RX_LINK_ADDR,
20 slc1tx_link: SLC1TX_LINK,
21 slc1tx_link_addr: SLC1TX_LINK_ADDR,
22 slcintvec_tohost: SLCINTVEC_TOHOST,
23 _reserved16: [u8; 0x04],
24 slc0token1: SLC0TOKEN1,
25 _reserved17: [u8; 0x04],
26 slc1token1: SLC1TOKEN1,
27 slcconf1: SLCCONF1,
28 _reserved19: [u8; 0x34],
29 slc_rx_dscr_conf: SLC_RX_DSCR_CONF,
30 _reserved20: [u8; 0x48],
31 slc0_len_conf: SLC0_LEN_CONF,
32 slc0_length: SLC0_LENGTH,
33 _reserved22: [u8; 0x50],
34 slc1int_st1: SLC1INT_ST1,
35 slc1int_ena1: SLC1INT_ENA1,
36 slc0_tx_sharemem_start: SLC0_TX_SHAREMEM_START,
37 slc0_tx_sharemem_end: SLC0_TX_SHAREMEM_END,
38 slc0_rx_sharemem_start: SLC0_RX_SHAREMEM_START,
39 slc0_rx_sharemem_end: SLC0_RX_SHAREMEM_END,
40 slc1_tx_sharemem_start: SLC1_TX_SHAREMEM_START,
41 slc1_tx_sharemem_end: SLC1_TX_SHAREMEM_END,
42 slc1_rx_sharemem_start: SLC1_RX_SHAREMEM_START,
43 slc1_rx_sharemem_end: SLC1_RX_SHAREMEM_END,
44 _reserved32: [u8; 0x08],
45 slc_burst_len: SLC_BURST_LEN,
46}
47impl RegisterBlock {
48 #[doc = "0x00 - DMA configuration"]
49 #[inline(always)]
50 pub const fn slcconf0(&self) -> &SLCCONF0 {
51 &self.slcconf0
52 }
53 #[doc = "0x04 - SLC0 to slave raw interrupt status"]
54 #[inline(always)]
55 pub const fn slc0int_raw(&self) -> &SLC0INT_RAW {
56 &self.slc0int_raw
57 }
58 #[doc = "0x08 - SLC0 to slave masked interrupt status"]
59 #[inline(always)]
60 pub const fn slc0int_st(&self) -> &SLC0INT_ST {
61 &self.slc0int_st
62 }
63 #[doc = "0x0c - SLC0 to slave interrupt enable"]
64 #[inline(always)]
65 pub const fn slc0int_ena(&self) -> &SLC0INT_ENA {
66 &self.slc0int_ena
67 }
68 #[doc = "0x10 - SLC0 to slave interrupt clear"]
69 #[inline(always)]
70 pub const fn slc0int_clr(&self) -> &SLC0INT_CLR {
71 &self.slc0int_clr
72 }
73 #[doc = "0x14 - SLC1 to slave raw interrupt status"]
74 #[inline(always)]
75 pub const fn slc1int_raw(&self) -> &SLC1INT_RAW {
76 &self.slc1int_raw
77 }
78 #[doc = "0x20 - SLC1 to slave interrupt clear"]
79 #[inline(always)]
80 pub const fn slc1int_clr(&self) -> &SLC1INT_CLR {
81 &self.slc1int_clr
82 }
83 #[doc = "0x3c - SLC0 RX linked list configuration"]
84 #[inline(always)]
85 pub const fn slc0rx_link(&self) -> &SLC0RX_LINK {
86 &self.slc0rx_link
87 }
88 #[doc = "0x40 - SLC0 RX linked list address"]
89 #[inline(always)]
90 pub const fn slc0rx_link_addr(&self) -> &SLC0RX_LINK_ADDR {
91 &self.slc0rx_link_addr
92 }
93 #[doc = "0x44 - SLC0 TX linked list configuration"]
94 #[inline(always)]
95 pub const fn slc0tx_link(&self) -> &SLC0TX_LINK {
96 &self.slc0tx_link
97 }
98 #[doc = "0x48 - SLC0 TX linked list address"]
99 #[inline(always)]
100 pub const fn slc0tx_link_addr(&self) -> &SLC0TX_LINK_ADDR {
101 &self.slc0tx_link_addr
102 }
103 #[doc = "0x4c - SLC1 RX linked list configuration"]
104 #[inline(always)]
105 pub const fn slc1rx_link(&self) -> &SLC1RX_LINK {
106 &self.slc1rx_link
107 }
108 #[doc = "0x50 - SLC1 RX linked list address"]
109 #[inline(always)]
110 pub const fn slc1rx_link_addr(&self) -> &SLC1RX_LINK_ADDR {
111 &self.slc1rx_link_addr
112 }
113 #[doc = "0x54 - SLC1 TX linked list configuration"]
114 #[inline(always)]
115 pub const fn slc1tx_link(&self) -> &SLC1TX_LINK {
116 &self.slc1tx_link
117 }
118 #[doc = "0x58 - SLC1 TX linked list address"]
119 #[inline(always)]
120 pub const fn slc1tx_link_addr(&self) -> &SLC1TX_LINK_ADDR {
121 &self.slc1tx_link_addr
122 }
123 #[doc = "0x5c - Slave to host interrupt vector set"]
124 #[inline(always)]
125 pub const fn slcintvec_tohost(&self) -> &SLCINTVEC_TOHOST {
126 &self.slcintvec_tohost
127 }
128 #[doc = "0x64 - SLC0 receiving buffer configuration"]
129 #[inline(always)]
130 pub const fn slc0token1(&self) -> &SLC0TOKEN1 {
131 &self.slc0token1
132 }
133 #[doc = "0x6c - SLC1 receiving buffer configuration"]
134 #[inline(always)]
135 pub const fn slc1token1(&self) -> &SLC1TOKEN1 {
136 &self.slc1token1
137 }
138 #[doc = "0x70 - DMA configuration"]
139 #[inline(always)]
140 pub const fn slcconf1(&self) -> &SLCCONF1 {
141 &self.slcconf1
142 }
143 #[doc = "0xa8 - DMA slave to host configuration register"]
144 #[inline(always)]
145 pub const fn slc_rx_dscr_conf(&self) -> &SLC_RX_DSCR_CONF {
146 &self.slc_rx_dscr_conf
147 }
148 #[doc = "0xf4 - Length control of transmitting packets"]
149 #[inline(always)]
150 pub const fn slc0_len_conf(&self) -> &SLC0_LEN_CONF {
151 &self.slc0_len_conf
152 }
153 #[doc = "0xf8 - Length of transmitting packets"]
154 #[inline(always)]
155 pub const fn slc0_length(&self) -> &SLC0_LENGTH {
156 &self.slc0_length
157 }
158 #[doc = "0x14c - SLC1 to slave masked interrupt status"]
159 #[inline(always)]
160 pub const fn slc1int_st1(&self) -> &SLC1INT_ST1 {
161 &self.slc1int_st1
162 }
163 #[doc = "0x150 - SLC1 to slave interrupt enable"]
164 #[inline(always)]
165 pub const fn slc1int_ena1(&self) -> &SLC1INT_ENA1 {
166 &self.slc1int_ena1
167 }
168 #[doc = "0x154 - SLC0 AHB TX start address range"]
169 #[inline(always)]
170 pub const fn slc0_tx_sharemem_start(&self) -> &SLC0_TX_SHAREMEM_START {
171 &self.slc0_tx_sharemem_start
172 }
173 #[doc = "0x158 - SLC0 AHB TX end address range"]
174 #[inline(always)]
175 pub const fn slc0_tx_sharemem_end(&self) -> &SLC0_TX_SHAREMEM_END {
176 &self.slc0_tx_sharemem_end
177 }
178 #[doc = "0x15c - SLC0 AHB RX start address range"]
179 #[inline(always)]
180 pub const fn slc0_rx_sharemem_start(&self) -> &SLC0_RX_SHAREMEM_START {
181 &self.slc0_rx_sharemem_start
182 }
183 #[doc = "0x160 - SLC0 AHB RX end address range"]
184 #[inline(always)]
185 pub const fn slc0_rx_sharemem_end(&self) -> &SLC0_RX_SHAREMEM_END {
186 &self.slc0_rx_sharemem_end
187 }
188 #[doc = "0x164 - SLC1 AHB TX start address range"]
189 #[inline(always)]
190 pub const fn slc1_tx_sharemem_start(&self) -> &SLC1_TX_SHAREMEM_START {
191 &self.slc1_tx_sharemem_start
192 }
193 #[doc = "0x168 - SLC1 AHB TX end address range"]
194 #[inline(always)]
195 pub const fn slc1_tx_sharemem_end(&self) -> &SLC1_TX_SHAREMEM_END {
196 &self.slc1_tx_sharemem_end
197 }
198 #[doc = "0x16c - SLC1 AHB RX start address range"]
199 #[inline(always)]
200 pub const fn slc1_rx_sharemem_start(&self) -> &SLC1_RX_SHAREMEM_START {
201 &self.slc1_rx_sharemem_start
202 }
203 #[doc = "0x170 - SLC1 AHB RX end address range"]
204 #[inline(always)]
205 pub const fn slc1_rx_sharemem_end(&self) -> &SLC1_RX_SHAREMEM_END {
206 &self.slc1_rx_sharemem_end
207 }
208 #[doc = "0x17c - DMA AHB burst type configuration"]
209 #[inline(always)]
210 pub const fn slc_burst_len(&self) -> &SLC_BURST_LEN {
211 &self.slc_burst_len
212 }
213}
214#[doc = "SLCCONF0 (rw) register accessor: DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcconf0`] module"]
215pub type SLCCONF0 = crate::Reg<slcconf0::SLCCONF0_SPEC>;
216#[doc = "DMA configuration"]
217pub mod slcconf0;
218#[doc = "SLC0RX_LINK (rw) register accessor: SLC0 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0rx_link`] module"]
219pub type SLC0RX_LINK = crate::Reg<slc0rx_link::SLC0RX_LINK_SPEC>;
220#[doc = "SLC0 RX linked list configuration"]
221pub mod slc0rx_link;
222#[doc = "SLC0RX_LINK_ADDR (rw) register accessor: SLC0 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0rx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0rx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0rx_link_addr`] module"]
223pub type SLC0RX_LINK_ADDR = crate::Reg<slc0rx_link_addr::SLC0RX_LINK_ADDR_SPEC>;
224#[doc = "SLC0 RX linked list address"]
225pub mod slc0rx_link_addr;
226#[doc = "SLC0TX_LINK (rw) register accessor: SLC0 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0tx_link`] module"]
227pub type SLC0TX_LINK = crate::Reg<slc0tx_link::SLC0TX_LINK_SPEC>;
228#[doc = "SLC0 TX linked list configuration"]
229pub mod slc0tx_link;
230#[doc = "SLC0TX_LINK_ADDR (rw) register accessor: SLC0 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0tx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0tx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0tx_link_addr`] module"]
231pub type SLC0TX_LINK_ADDR = crate::Reg<slc0tx_link_addr::SLC0TX_LINK_ADDR_SPEC>;
232#[doc = "SLC0 TX linked list address"]
233pub mod slc0tx_link_addr;
234#[doc = "SLC1RX_LINK (rw) register accessor: SLC1 RX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1rx_link`] module"]
235pub type SLC1RX_LINK = crate::Reg<slc1rx_link::SLC1RX_LINK_SPEC>;
236#[doc = "SLC1 RX linked list configuration"]
237pub mod slc1rx_link;
238#[doc = "SLC1RX_LINK_ADDR (rw) register accessor: SLC1 RX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1rx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1rx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1rx_link_addr`] module"]
239pub type SLC1RX_LINK_ADDR = crate::Reg<slc1rx_link_addr::SLC1RX_LINK_ADDR_SPEC>;
240#[doc = "SLC1 RX linked list address"]
241pub mod slc1rx_link_addr;
242#[doc = "SLC1TX_LINK (rw) register accessor: SLC1 TX linked list configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1tx_link`] module"]
243pub type SLC1TX_LINK = crate::Reg<slc1tx_link::SLC1TX_LINK_SPEC>;
244#[doc = "SLC1 TX linked list configuration"]
245pub mod slc1tx_link;
246#[doc = "SLC1TX_LINK_ADDR (rw) register accessor: SLC1 TX linked list address\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1tx_link_addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1tx_link_addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1tx_link_addr`] module"]
247pub type SLC1TX_LINK_ADDR = crate::Reg<slc1tx_link_addr::SLC1TX_LINK_ADDR_SPEC>;
248#[doc = "SLC1 TX linked list address"]
249pub mod slc1tx_link_addr;
250#[doc = "SLC0TOKEN1 (rw) register accessor: SLC0 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0token1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0token1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0token1`] module"]
251pub type SLC0TOKEN1 = crate::Reg<slc0token1::SLC0TOKEN1_SPEC>;
252#[doc = "SLC0 receiving buffer configuration"]
253pub mod slc0token1;
254#[doc = "SLC1TOKEN1 (rw) register accessor: SLC1 receiving buffer configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1token1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1token1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1token1`] module"]
255pub type SLC1TOKEN1 = crate::Reg<slc1token1::SLC1TOKEN1_SPEC>;
256#[doc = "SLC1 receiving buffer configuration"]
257pub mod slc1token1;
258#[doc = "SLCCONF1 (rw) register accessor: DMA configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slcconf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcconf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcconf1`] module"]
259pub type SLCCONF1 = crate::Reg<slcconf1::SLCCONF1_SPEC>;
260#[doc = "DMA configuration"]
261pub mod slcconf1;
262#[doc = "SLC_RX_DSCR_CONF (rw) register accessor: DMA slave to host configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_rx_dscr_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_rx_dscr_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_rx_dscr_conf`] module"]
263pub type SLC_RX_DSCR_CONF = crate::Reg<slc_rx_dscr_conf::SLC_RX_DSCR_CONF_SPEC>;
264#[doc = "DMA slave to host configuration register"]
265pub mod slc_rx_dscr_conf;
266#[doc = "SLC0_LEN_CONF (w) register accessor: Length control of transmitting packets\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_len_conf::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_len_conf`] module"]
267pub type SLC0_LEN_CONF = crate::Reg<slc0_len_conf::SLC0_LEN_CONF_SPEC>;
268#[doc = "Length control of transmitting packets"]
269pub mod slc0_len_conf;
270#[doc = "SLC0_TX_SHAREMEM_START (rw) register accessor: SLC0 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_tx_sharemem_start`] module"]
271pub type SLC0_TX_SHAREMEM_START = crate::Reg<slc0_tx_sharemem_start::SLC0_TX_SHAREMEM_START_SPEC>;
272#[doc = "SLC0 AHB TX start address range"]
273pub mod slc0_tx_sharemem_start;
274#[doc = "SLC0_TX_SHAREMEM_END (rw) register accessor: SLC0 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_tx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_tx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_tx_sharemem_end`] module"]
275pub type SLC0_TX_SHAREMEM_END = crate::Reg<slc0_tx_sharemem_end::SLC0_TX_SHAREMEM_END_SPEC>;
276#[doc = "SLC0 AHB TX end address range"]
277pub mod slc0_tx_sharemem_end;
278#[doc = "SLC0_RX_SHAREMEM_START (rw) register accessor: SLC0 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_rx_sharemem_start`] module"]
279pub type SLC0_RX_SHAREMEM_START = crate::Reg<slc0_rx_sharemem_start::SLC0_RX_SHAREMEM_START_SPEC>;
280#[doc = "SLC0 AHB RX start address range"]
281pub mod slc0_rx_sharemem_start;
282#[doc = "SLC0_RX_SHAREMEM_END (rw) register accessor: SLC0 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_rx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0_rx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_rx_sharemem_end`] module"]
283pub type SLC0_RX_SHAREMEM_END = crate::Reg<slc0_rx_sharemem_end::SLC0_RX_SHAREMEM_END_SPEC>;
284#[doc = "SLC0 AHB RX end address range"]
285pub mod slc0_rx_sharemem_end;
286#[doc = "SLC1_TX_SHAREMEM_START (rw) register accessor: SLC1 AHB TX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_tx_sharemem_start`] module"]
287pub type SLC1_TX_SHAREMEM_START = crate::Reg<slc1_tx_sharemem_start::SLC1_TX_SHAREMEM_START_SPEC>;
288#[doc = "SLC1 AHB TX start address range"]
289pub mod slc1_tx_sharemem_start;
290#[doc = "SLC1_TX_SHAREMEM_END (rw) register accessor: SLC1 AHB TX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_tx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_tx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_tx_sharemem_end`] module"]
291pub type SLC1_TX_SHAREMEM_END = crate::Reg<slc1_tx_sharemem_end::SLC1_TX_SHAREMEM_END_SPEC>;
292#[doc = "SLC1 AHB TX end address range"]
293pub mod slc1_tx_sharemem_end;
294#[doc = "SLC1_RX_SHAREMEM_START (rw) register accessor: SLC1 AHB RX start address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_start::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_start::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_rx_sharemem_start`] module"]
295pub type SLC1_RX_SHAREMEM_START = crate::Reg<slc1_rx_sharemem_start::SLC1_RX_SHAREMEM_START_SPEC>;
296#[doc = "SLC1 AHB RX start address range"]
297pub mod slc1_rx_sharemem_start;
298#[doc = "SLC1_RX_SHAREMEM_END (rw) register accessor: SLC1 AHB RX end address range\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1_rx_sharemem_end::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1_rx_sharemem_end::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1_rx_sharemem_end`] module"]
299pub type SLC1_RX_SHAREMEM_END = crate::Reg<slc1_rx_sharemem_end::SLC1_RX_SHAREMEM_END_SPEC>;
300#[doc = "SLC1 AHB RX end address range"]
301pub mod slc1_rx_sharemem_end;
302#[doc = "SLC_BURST_LEN (rw) register accessor: DMA AHB burst type configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`slc_burst_len::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc_burst_len::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc_burst_len`] module"]
303pub type SLC_BURST_LEN = crate::Reg<slc_burst_len::SLC_BURST_LEN_SPEC>;
304#[doc = "DMA AHB burst type configuration"]
305pub mod slc_burst_len;
306#[doc = "SLC0INT_RAW (rw) register accessor: SLC0 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_raw`] module"]
307pub type SLC0INT_RAW = crate::Reg<slc0int_raw::SLC0INT_RAW_SPEC>;
308#[doc = "SLC0 to slave raw interrupt status"]
309pub mod slc0int_raw;
310#[doc = "SLC0INT_ST (r) register accessor: SLC0 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_st`] module"]
311pub type SLC0INT_ST = crate::Reg<slc0int_st::SLC0INT_ST_SPEC>;
312#[doc = "SLC0 to slave masked interrupt status"]
313pub mod slc0int_st;
314#[doc = "SLC0INT_ENA (rw) register accessor: SLC0 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_ena`] module"]
315pub type SLC0INT_ENA = crate::Reg<slc0int_ena::SLC0INT_ENA_SPEC>;
316#[doc = "SLC0 to slave interrupt enable"]
317pub mod slc0int_ena;
318#[doc = "SLC0INT_CLR (w) register accessor: SLC0 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc0int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0int_clr`] module"]
319pub type SLC0INT_CLR = crate::Reg<slc0int_clr::SLC0INT_CLR_SPEC>;
320#[doc = "SLC0 to slave interrupt clear"]
321pub mod slc0int_clr;
322#[doc = "SLC1INT_RAW (rw) register accessor: SLC1 to slave raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_raw`] module"]
323pub type SLC1INT_RAW = crate::Reg<slc1int_raw::SLC1INT_RAW_SPEC>;
324#[doc = "SLC1 to slave raw interrupt status"]
325pub mod slc1int_raw;
326#[doc = "SLC1INT_CLR (w) register accessor: SLC1 to slave interrupt clear\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_clr`] module"]
327pub type SLC1INT_CLR = crate::Reg<slc1int_clr::SLC1INT_CLR_SPEC>;
328#[doc = "SLC1 to slave interrupt clear"]
329pub mod slc1int_clr;
330#[doc = "SLCINTVEC_TOHOST (w) register accessor: Slave to host interrupt vector set\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slcintvec_tohost::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slcintvec_tohost`] module"]
331pub type SLCINTVEC_TOHOST = crate::Reg<slcintvec_tohost::SLCINTVEC_TOHOST_SPEC>;
332#[doc = "Slave to host interrupt vector set"]
333pub mod slcintvec_tohost;
334#[doc = "SLC1INT_ST1 (r) register accessor: SLC1 to slave masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_st1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_st1`] module"]
335pub type SLC1INT_ST1 = crate::Reg<slc1int_st1::SLC1INT_ST1_SPEC>;
336#[doc = "SLC1 to slave masked interrupt status"]
337pub mod slc1int_st1;
338#[doc = "SLC1INT_ENA1 (rw) register accessor: SLC1 to slave interrupt enable\n\nYou can [`read`](crate::Reg::read) this register and get [`slc1int_ena1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`slc1int_ena1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc1int_ena1`] module"]
339pub type SLC1INT_ENA1 = crate::Reg<slc1int_ena1::SLC1INT_ENA1_SPEC>;
340#[doc = "SLC1 to slave interrupt enable"]
341pub mod slc1int_ena1;
342#[doc = "SLC0_LENGTH (r) register accessor: Length of transmitting packets\n\nYou can [`read`](crate::Reg::read) this register and get [`slc0_length::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@slc0_length`] module"]
343pub type SLC0_LENGTH = crate::Reg<slc0_length::SLC0_LENGTH_SPEC>;
344#[doc = "Length of transmitting packets"]
345pub mod slc0_length;