esp32c6/gpio/
func_out_sel_cfg.rs

1#[doc = "Register `FUNC%s_OUT_SEL_CFG` reader"]
2pub type R = crate::R<FUNC_OUT_SEL_CFG_SPEC>;
3#[doc = "Register `FUNC%s_OUT_SEL_CFG` writer"]
4pub type W = crate::W<FUNC_OUT_SEL_CFG_SPEC>;
5#[doc = "Field `OUT_SEL` reader - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
6pub type OUT_SEL_R = crate::FieldReader;
7#[doc = "Field `OUT_SEL` writer - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
8pub type OUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `INV_SEL` reader - set this bit to invert output signal.1:invert.0:not invert."]
10pub type INV_SEL_R = crate::BitReader;
11#[doc = "Field `INV_SEL` writer - set this bit to invert output signal.1:invert.0:not invert."]
12pub type INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `OEN_SEL` reader - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."]
14pub type OEN_SEL_R = crate::BitReader;
15#[doc = "Field `OEN_SEL` writer - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."]
16pub type OEN_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `OEN_INV_SEL` reader - set this bit to invert output enable signal.1:invert.0:not invert."]
18pub type OEN_INV_SEL_R = crate::BitReader;
19#[doc = "Field `OEN_INV_SEL` writer - set this bit to invert output enable signal.1:invert.0:not invert."]
20pub type OEN_INV_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bits 0:7 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
23    #[inline(always)]
24    pub fn out_sel(&self) -> OUT_SEL_R {
25        OUT_SEL_R::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bit 8 - set this bit to invert output signal.1:invert.0:not invert."]
28    #[inline(always)]
29    pub fn inv_sel(&self) -> INV_SEL_R {
30        INV_SEL_R::new(((self.bits >> 8) & 1) != 0)
31    }
32    #[doc = "Bit 9 - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."]
33    #[inline(always)]
34    pub fn oen_sel(&self) -> OEN_SEL_R {
35        OEN_SEL_R::new(((self.bits >> 9) & 1) != 0)
36    }
37    #[doc = "Bit 10 - set this bit to invert output enable signal.1:invert.0:not invert."]
38    #[inline(always)]
39    pub fn oen_inv_sel(&self) -> OEN_INV_SEL_R {
40        OEN_INV_SEL_R::new(((self.bits >> 10) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("FUNC_OUT_SEL_CFG")
47            .field("out_sel", &self.out_sel())
48            .field("inv_sel", &self.inv_sel())
49            .field("oen_sel", &self.oen_sel())
50            .field("oen_inv_sel", &self.oen_inv_sel())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7 - The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO\\[n\\] equals input of peripheral\\[s\\]. s=128: output of GPIO\\[n\\] equals GPIO_OUT_REG\\[n\\]."]
56    #[inline(always)]
57    pub fn out_sel(&mut self) -> OUT_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
58        OUT_SEL_W::new(self, 0)
59    }
60    #[doc = "Bit 8 - set this bit to invert output signal.1:invert.0:not invert."]
61    #[inline(always)]
62    pub fn inv_sel(&mut self) -> INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
63        INV_SEL_W::new(self, 8)
64    }
65    #[doc = "Bit 9 - set this bit to select output enable signal.1:use GPIO_ENABLE_REG\\[n\\] as output enable signal.0:use peripheral output enable signal."]
66    #[inline(always)]
67    pub fn oen_sel(&mut self) -> OEN_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
68        OEN_SEL_W::new(self, 9)
69    }
70    #[doc = "Bit 10 - set this bit to invert output enable signal.1:invert.0:not invert."]
71    #[inline(always)]
72    pub fn oen_inv_sel(&mut self) -> OEN_INV_SEL_W<FUNC_OUT_SEL_CFG_SPEC> {
73        OEN_INV_SEL_W::new(self, 10)
74    }
75}
76#[doc = "GPIO output function select register\n\nYou can [`read`](crate::Reg::read) this register and get [`func_out_sel_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`func_out_sel_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct FUNC_OUT_SEL_CFG_SPEC;
78impl crate::RegisterSpec for FUNC_OUT_SEL_CFG_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`func_out_sel_cfg::R`](R) reader structure"]
82impl crate::Readable for FUNC_OUT_SEL_CFG_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`func_out_sel_cfg::W`](W) writer structure"]
84impl crate::Writable for FUNC_OUT_SEL_CFG_SPEC {
85    type Safety = crate::Unsafe;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets FUNC%s_OUT_SEL_CFG to value 0x80"]
90impl crate::Resettable for FUNC_OUT_SEL_CFG_SPEC {
91    const RESET_VALUE: u32 = 0x80;
92}
esp32c6/gpio/func_out_sel_cfg.rs

esp32c6/gpio/
func_out_sel_cfg.rs
