esp32c6/extmem/
l2_cache_sync_preload_int_raw.rs

1#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_RAW` reader"]
2pub type R = crate::R<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC>;
3#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_RAW` writer"]
4pub type W = crate::W<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC>;
5#[doc = "Field `L2_CACHE_PLD_DONE_INT_RAW` reader - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
6pub type L2_CACHE_PLD_DONE_INT_RAW_R = crate::BitReader;
7#[doc = "Field `L2_CACHE_PLD_DONE_INT_RAW` writer - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
8pub type L2_CACHE_PLD_DONE_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L2_CACHE_PLD_ERR_INT_RAW` reader - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."]
10pub type L2_CACHE_PLD_ERR_INT_RAW_R = crate::BitReader;
11#[doc = "Field `L2_CACHE_PLD_ERR_INT_RAW` writer - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."]
12pub type L2_CACHE_PLD_ERR_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
15    #[inline(always)]
16    pub fn l2_cache_pld_done_int_raw(&self) -> L2_CACHE_PLD_DONE_INT_RAW_R {
17        L2_CACHE_PLD_DONE_INT_RAW_R::new(((self.bits >> 5) & 1) != 0)
18    }
19    #[doc = "Bit 12 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."]
20    #[inline(always)]
21    pub fn l2_cache_pld_err_int_raw(&self) -> L2_CACHE_PLD_ERR_INT_RAW_R {
22        L2_CACHE_PLD_ERR_INT_RAW_R::new(((self.bits >> 12) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_RAW")
29            .field(
30                "l2_cache_pld_done_int_raw",
31                &self.l2_cache_pld_done_int_raw(),
32            )
33            .field("l2_cache_pld_err_int_raw", &self.l2_cache_pld_err_int_raw())
34            .finish()
35    }
36}
37impl W {
38    #[doc = "Bit 5 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done."]
39    #[inline(always)]
40    pub fn l2_cache_pld_done_int_raw(
41        &mut self,
42    ) -> L2_CACHE_PLD_DONE_INT_RAW_W<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC> {
43        L2_CACHE_PLD_DONE_INT_RAW_W::new(self, 5)
44    }
45    #[doc = "Bit 12 - The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs."]
46    #[inline(always)]
47    pub fn l2_cache_pld_err_int_raw(
48        &mut self,
49    ) -> L2_CACHE_PLD_ERR_INT_RAW_W<L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC> {
50        L2_CACHE_PLD_ERR_INT_RAW_W::new(self, 12)
51    }
52}
53#[doc = "Sync Preload operation Interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`l2_cache_sync_preload_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l2_cache_sync_preload_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC;
55impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`l2_cache_sync_preload_int_raw::R`](R) reader structure"]
59impl crate::Readable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC {}
60#[doc = "`write(|w| ..)` method takes [`l2_cache_sync_preload_int_raw::W`](W) writer structure"]
61impl crate::Writable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC {
62    type Safety = crate::Unsafe;
63    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
64    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
65}
66#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_RAW to value 0"]
67impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC {
68    const RESET_VALUE: u32 = 0;
69}
esp32c6/extmem/l2_cache_sync_preload_int_raw.rs

esp32c6/extmem/
l2_cache_sync_preload_int_raw.rs
