esp32c6/extmem/
l1_dcache_preload_addr.rs

1#[doc = "Register `L1_DCACHE_PRELOAD_ADDR` reader"]
2pub type R = crate::R<L1_DCACHE_PRELOAD_ADDR_SPEC>;
3#[doc = "Register `L1_DCACHE_PRELOAD_ADDR` writer"]
4pub type W = crate::W<L1_DCACHE_PRELOAD_ADDR_SPEC>;
5#[doc = "Field `L1_CACHE_PRELOAD_ADDR` reader - Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG"]
6pub type L1_CACHE_PRELOAD_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `L1_CACHE_PRELOAD_ADDR` writer - Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG"]
8pub type L1_CACHE_PRELOAD_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG"]
11    #[inline(always)]
12    pub fn l1_cache_preload_addr(&self) -> L1_CACHE_PRELOAD_ADDR_R {
13        L1_CACHE_PRELOAD_ADDR_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("L1_DCACHE_PRELOAD_ADDR")
20            .field("l1_cache_preload_addr", &self.l1_cache_preload_addr())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:31 - Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG"]
26    #[inline(always)]
27    pub fn l1_cache_preload_addr(
28        &mut self,
29    ) -> L1_CACHE_PRELOAD_ADDR_W<L1_DCACHE_PRELOAD_ADDR_SPEC> {
30        L1_CACHE_PRELOAD_ADDR_W::new(self, 0)
31    }
32}
33#[doc = "L1 Cache preload address configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_dcache_preload_addr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_dcache_preload_addr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
34pub struct L1_DCACHE_PRELOAD_ADDR_SPEC;
35impl crate::RegisterSpec for L1_DCACHE_PRELOAD_ADDR_SPEC {
36    type Ux = u32;
37}
38#[doc = "`read()` method returns [`l1_dcache_preload_addr::R`](R) reader structure"]
39impl crate::Readable for L1_DCACHE_PRELOAD_ADDR_SPEC {}
40#[doc = "`write(|w| ..)` method takes [`l1_dcache_preload_addr::W`](W) writer structure"]
41impl crate::Writable for L1_DCACHE_PRELOAD_ADDR_SPEC {
42    type Safety = crate::Unsafe;
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
45}
46#[doc = "`reset()` method sets L1_DCACHE_PRELOAD_ADDR to value 0"]
47impl crate::Resettable for L1_DCACHE_PRELOAD_ADDR_SPEC {
48    const RESET_VALUE: u32 = 0;
49}
esp32c6/extmem/l1_dcache_preload_addr.rs

esp32c6/extmem/
l1_dcache_preload_addr.rs
