Expand description
L1 data Cache(L1-Cache) control register
Structs§
- L1_
CACHE_ CTRL_ SPEC - L1 data Cache(L1-Cache) control register
Type Aliases§
- L1_
CACHE_ SHUT_ BUS0_ R - Field
L1_CACHE_SHUT_BUS0
reader - The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable - L1_
CACHE_ SHUT_ BUS0_ W - Field
L1_CACHE_SHUT_BUS0
writer - The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable - L1_
CACHE_ SHUT_ BUS1_ R - Field
L1_CACHE_SHUT_BUS1
reader - The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable - L1_
CACHE_ SHUT_ BUS1_ W - Field
L1_CACHE_SHUT_BUS1
writer - The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable - L1_
CACHE_ SHUT_ DBUS2_ R - Field
L1_CACHE_SHUT_DBUS2
reader - Reserved - L1_
CACHE_ SHUT_ DBUS3_ R - Field
L1_CACHE_SHUT_DBUS3
reader - Reserved - L1_
CACHE_ SHUT_ DMA_ R - Field
L1_CACHE_SHUT_DMA
reader - The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable - L1_
CACHE_ UNDEF_ OP_ R - Field
L1_CACHE_UNDEF_OP
reader - Reserved - L1_
CACHE_ UNDEF_ OP_ W - Field
L1_CACHE_UNDEF_OP
writer - Reserved - R
- Register
L1_CACHE_CTRL
reader - W
- Register
L1_CACHE_CTRL
writer