Module ch

Cluster Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?

Modules

in_conf0

Configure 0 register of Rx channel 0

in_conf1

Configure 1 register of Rx channel 0

in_dscr

Current inlink descriptor address of Rx channel 0

in_dscr_bf0

The last inlink descriptor address of Rx channel 0

in_dscr_bf1

The second-to-last inlink descriptor address of Rx channel 0

in_err_eof_des_addr

Inlink descriptor address when errors occur of Rx channel 0

in_link

Link descriptor configure and control register of Rx channel 0

in_peri_sel

Peripheral selection of Rx channel 0

in_pop

Pop control register of Rx channel 0

in_pri

Priority register of Rx channel 0

in_state

Receive status of Rx channel 0

in_suc_eof_des_addr

Inlink descriptor address when EOF occurs of Rx channel 0

infifo_status

Receive FIFO status of Rx channel 0

out_conf0

Configure 0 register of Tx channel 1

out_conf1

Configure 1 register of Tx channel 0

out_dscr

Current inlink descriptor address of Tx channel 0

out_dscr_bf0

The last inlink descriptor address of Tx channel 0

out_dscr_bf1

The second-to-last inlink descriptor address of Tx channel 0

out_eof_bfr_des_addr

The last outlink descriptor address when EOF occurs of Tx channel 0

out_eof_des_addr

Outlink descriptor address when EOF occurs of Tx channel 0

out_link

Link descriptor configure and control register of Tx channel 0

out_peri_sel

Peripheral selection of Tx channel 0

out_pri

Priority register of Tx channel 0.

out_push

Push control register of Rx channel 0

out_state

Transmit status of Tx channel 0

outfifo_status

Transmit FIFO status of Tx channel 0

Structs

CH

Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?

Type Aliases

INFIFO_STATUS

INFIFO_STATUS (r) register accessor: Receive FIFO status of Rx channel 0

IN_CONF0

IN_CONF0 (rw) register accessor: Configure 0 register of Rx channel 0

IN_CONF1

IN_CONF1 (rw) register accessor: Configure 1 register of Rx channel 0

IN_DSCR

IN_DSCR (r) register accessor: Current inlink descriptor address of Rx channel 0

IN_DSCR_BF0

IN_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Rx channel 0

IN_DSCR_BF1

IN_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Rx channel 0

IN_ERR_EOF_DES_ADDR

IN_ERR_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when errors occur of Rx channel 0

IN_LINK

IN_LINK (rw) register accessor: Link descriptor configure and control register of Rx channel 0

IN_PERI_SEL

IN_PERI_SEL (rw) register accessor: Peripheral selection of Rx channel 0

IN_POP

IN_POP (rw) register accessor: Pop control register of Rx channel 0

IN_PRI

IN_PRI (rw) register accessor: Priority register of Rx channel 0

IN_STATE

IN_STATE (r) register accessor: Receive status of Rx channel 0

IN_SUC_EOF_DES_ADDR

IN_SUC_EOF_DES_ADDR (r) register accessor: Inlink descriptor address when EOF occurs of Rx channel 0

OUTFIFO_STATUS

OUTFIFO_STATUS (r) register accessor: Transmit FIFO status of Tx channel 0

OUT_CONF0

OUT_CONF0 (rw) register accessor: Configure 0 register of Tx channel 1

OUT_CONF1

OUT_CONF1 (rw) register accessor: Configure 1 register of Tx channel 0

OUT_DSCR

OUT_DSCR (r) register accessor: Current inlink descriptor address of Tx channel 0

OUT_DSCR_BF0

OUT_DSCR_BF0 (r) register accessor: The last inlink descriptor address of Tx channel 0

OUT_DSCR_BF1

OUT_DSCR_BF1 (r) register accessor: The second-to-last inlink descriptor address of Tx channel 0

OUT_EOF_BFR_DES_ADDR

OUT_EOF_BFR_DES_ADDR (r) register accessor: The last outlink descriptor address when EOF occurs of Tx channel 0

OUT_EOF_DES_ADDR

OUT_EOF_DES_ADDR (r) register accessor: Outlink descriptor address when EOF occurs of Tx channel 0

OUT_LINK

OUT_LINK (rw) register accessor: Link descriptor configure and control register of Tx channel 0

OUT_PERI_SEL

OUT_PERI_SEL (rw) register accessor: Peripheral selection of Tx channel 0

OUT_PRI

OUT_PRI (rw) register accessor: Priority register of Tx channel 0.

OUT_PUSH

OUT_PUSH (rw) register accessor: Push control register of Rx channel 0

OUT_STATE

OUT_STATE (r) register accessor: Transmit status of Tx channel 0