1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 fifo: FIFO,
6 int_raw: INT_RAW,
7 int_st: INT_ST,
8 int_ena: INT_ENA,
9 int_clr: INT_CLR,
10 clkdiv: CLKDIV,
11 rx_filt: RX_FILT,
12 status: STATUS,
13 conf0: CONF0,
14 conf1: CONF1,
15 _reserved10: [u8; 0x04],
16 hwfc_conf: HWFC_CONF,
17 sleep_conf0: SLEEP_CONF0,
18 sleep_conf1: SLEEP_CONF1,
19 sleep_conf2: SLEEP_CONF2,
20 swfc_conf0: SWFC_CONF0,
21 swfc_conf1: SWFC_CONF1,
22 txbrk_conf: TXBRK_CONF,
23 idle_conf: IDLE_CONF,
24 rs485_conf: RS485_CONF,
25 at_cmd_precnt: AT_CMD_PRECNT,
26 at_cmd_postcnt: AT_CMD_POSTCNT,
27 at_cmd_gaptout: AT_CMD_GAPTOUT,
28 at_cmd_char: AT_CMD_CHAR,
29 mem_conf: MEM_CONF,
30 tout_conf: TOUT_CONF,
31 mem_tx_status: MEM_TX_STATUS,
32 mem_rx_status: MEM_RX_STATUS,
33 fsm_status: FSM_STATUS,
34 pospulse: POSPULSE,
35 negpulse: NEGPULSE,
36 lowpulse: LOWPULSE,
37 highpulse: HIGHPULSE,
38 rxd_cnt: RXD_CNT,
39 clk_conf: CLK_CONF,
40 date: DATE,
41 afifo_status: AFIFO_STATUS,
42 _reserved36: [u8; 0x04],
43 reg_update: REG_UPDATE,
44 id: ID,
45}
46impl RegisterBlock {
47 #[doc = "0x00 - FIFO data register"]
48 #[inline(always)]
49 pub const fn fifo(&self) -> &FIFO {
50 &self.fifo
51 }
52 #[doc = "0x04 - Raw interrupt status"]
53 #[inline(always)]
54 pub const fn int_raw(&self) -> &INT_RAW {
55 &self.int_raw
56 }
57 #[doc = "0x08 - Masked interrupt status"]
58 #[inline(always)]
59 pub const fn int_st(&self) -> &INT_ST {
60 &self.int_st
61 }
62 #[doc = "0x0c - Interrupt enable bits"]
63 #[inline(always)]
64 pub const fn int_ena(&self) -> &INT_ENA {
65 &self.int_ena
66 }
67 #[doc = "0x10 - Interrupt clear bits"]
68 #[inline(always)]
69 pub const fn int_clr(&self) -> &INT_CLR {
70 &self.int_clr
71 }
72 #[doc = "0x14 - Clock divider configuration"]
73 #[inline(always)]
74 pub const fn clkdiv(&self) -> &CLKDIV {
75 &self.clkdiv
76 }
77 #[doc = "0x18 - Rx Filter configuration"]
78 #[inline(always)]
79 pub const fn rx_filt(&self) -> &RX_FILT {
80 &self.rx_filt
81 }
82 #[doc = "0x1c - UART status register"]
83 #[inline(always)]
84 pub const fn status(&self) -> &STATUS {
85 &self.status
86 }
87 #[doc = "0x20 - a"]
88 #[inline(always)]
89 pub const fn conf0(&self) -> &CONF0 {
90 &self.conf0
91 }
92 #[doc = "0x24 - Configuration register 1"]
93 #[inline(always)]
94 pub const fn conf1(&self) -> &CONF1 {
95 &self.conf1
96 }
97 #[doc = "0x2c - Hardware flow-control configuration"]
98 #[inline(always)]
99 pub const fn hwfc_conf(&self) -> &HWFC_CONF {
100 &self.hwfc_conf
101 }
102 #[doc = "0x30 - UART sleep configure register 0"]
103 #[inline(always)]
104 pub const fn sleep_conf0(&self) -> &SLEEP_CONF0 {
105 &self.sleep_conf0
106 }
107 #[doc = "0x34 - UART sleep configure register 1"]
108 #[inline(always)]
109 pub const fn sleep_conf1(&self) -> &SLEEP_CONF1 {
110 &self.sleep_conf1
111 }
112 #[doc = "0x38 - UART sleep configure register 2"]
113 #[inline(always)]
114 pub const fn sleep_conf2(&self) -> &SLEEP_CONF2 {
115 &self.sleep_conf2
116 }
117 #[doc = "0x3c - Software flow-control character configuration"]
118 #[inline(always)]
119 pub const fn swfc_conf0(&self) -> &SWFC_CONF0 {
120 &self.swfc_conf0
121 }
122 #[doc = "0x40 - Software flow-control character configuration"]
123 #[inline(always)]
124 pub const fn swfc_conf1(&self) -> &SWFC_CONF1 {
125 &self.swfc_conf1
126 }
127 #[doc = "0x44 - Tx Break character configuration"]
128 #[inline(always)]
129 pub const fn txbrk_conf(&self) -> &TXBRK_CONF {
130 &self.txbrk_conf
131 }
132 #[doc = "0x48 - Frame-end idle configuration"]
133 #[inline(always)]
134 pub const fn idle_conf(&self) -> &IDLE_CONF {
135 &self.idle_conf
136 }
137 #[doc = "0x4c - RS485 mode configuration"]
138 #[inline(always)]
139 pub const fn rs485_conf(&self) -> &RS485_CONF {
140 &self.rs485_conf
141 }
142 #[doc = "0x50 - Pre-sequence timing configuration"]
143 #[inline(always)]
144 pub const fn at_cmd_precnt(&self) -> &AT_CMD_PRECNT {
145 &self.at_cmd_precnt
146 }
147 #[doc = "0x54 - Post-sequence timing configuration"]
148 #[inline(always)]
149 pub const fn at_cmd_postcnt(&self) -> &AT_CMD_POSTCNT {
150 &self.at_cmd_postcnt
151 }
152 #[doc = "0x58 - Timeout configuration"]
153 #[inline(always)]
154 pub const fn at_cmd_gaptout(&self) -> &AT_CMD_GAPTOUT {
155 &self.at_cmd_gaptout
156 }
157 #[doc = "0x5c - AT escape sequence detection configuration"]
158 #[inline(always)]
159 pub const fn at_cmd_char(&self) -> &AT_CMD_CHAR {
160 &self.at_cmd_char
161 }
162 #[doc = "0x60 - UART memory power configuration"]
163 #[inline(always)]
164 pub const fn mem_conf(&self) -> &MEM_CONF {
165 &self.mem_conf
166 }
167 #[doc = "0x64 - UART threshold and allocation configuration"]
168 #[inline(always)]
169 pub const fn tout_conf(&self) -> &TOUT_CONF {
170 &self.tout_conf
171 }
172 #[doc = "0x68 - Tx-SRAM write and read offset address."]
173 #[inline(always)]
174 pub const fn mem_tx_status(&self) -> &MEM_TX_STATUS {
175 &self.mem_tx_status
176 }
177 #[doc = "0x6c - Rx-SRAM write and read offset address."]
178 #[inline(always)]
179 pub const fn mem_rx_status(&self) -> &MEM_RX_STATUS {
180 &self.mem_rx_status
181 }
182 #[doc = "0x70 - UART transmit and receive status."]
183 #[inline(always)]
184 pub const fn fsm_status(&self) -> &FSM_STATUS {
185 &self.fsm_status
186 }
187 #[doc = "0x74 - Autobaud high pulse register"]
188 #[inline(always)]
189 pub const fn pospulse(&self) -> &POSPULSE {
190 &self.pospulse
191 }
192 #[doc = "0x78 - Autobaud low pulse register"]
193 #[inline(always)]
194 pub const fn negpulse(&self) -> &NEGPULSE {
195 &self.negpulse
196 }
197 #[doc = "0x7c - Autobaud minimum low pulse duration register"]
198 #[inline(always)]
199 pub const fn lowpulse(&self) -> &LOWPULSE {
200 &self.lowpulse
201 }
202 #[doc = "0x80 - Autobaud minimum high pulse duration register"]
203 #[inline(always)]
204 pub const fn highpulse(&self) -> &HIGHPULSE {
205 &self.highpulse
206 }
207 #[doc = "0x84 - Autobaud edge change count register"]
208 #[inline(always)]
209 pub const fn rxd_cnt(&self) -> &RXD_CNT {
210 &self.rxd_cnt
211 }
212 #[doc = "0x88 - UART core clock configuration"]
213 #[inline(always)]
214 pub const fn clk_conf(&self) -> &CLK_CONF {
215 &self.clk_conf
216 }
217 #[doc = "0x8c - UART Version register"]
218 #[inline(always)]
219 pub const fn date(&self) -> &DATE {
220 &self.date
221 }
222 #[doc = "0x90 - UART AFIFO Status"]
223 #[inline(always)]
224 pub const fn afifo_status(&self) -> &AFIFO_STATUS {
225 &self.afifo_status
226 }
227 #[doc = "0x98 - UART Registers Configuration Update register"]
228 #[inline(always)]
229 pub const fn reg_update(&self) -> ®_UPDATE {
230 &self.reg_update
231 }
232 #[doc = "0x9c - UART ID register"]
233 #[inline(always)]
234 pub const fn id(&self) -> &ID {
235 &self.id
236 }
237}
238#[doc = "FIFO (rw) register accessor: FIFO data register\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo`] module"]
239pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
240#[doc = "FIFO data register"]
241pub mod fifo;
242#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
243pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
244#[doc = "Raw interrupt status"]
245pub mod int_raw;
246#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
247pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
248#[doc = "Masked interrupt status"]
249pub mod int_st;
250#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
251pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
252#[doc = "Interrupt enable bits"]
253pub mod int_ena;
254#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
255pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
256#[doc = "Interrupt clear bits"]
257pub mod int_clr;
258#[doc = "CLKDIV (rw) register accessor: Clock divider configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`] module"]
259pub type CLKDIV = crate::Reg<clkdiv::CLKDIV_SPEC>;
260#[doc = "Clock divider configuration"]
261pub mod clkdiv;
262#[doc = "RX_FILT (rw) register accessor: Rx Filter configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_filt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_filt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_filt`] module"]
263pub type RX_FILT = crate::Reg<rx_filt::RX_FILT_SPEC>;
264#[doc = "Rx Filter configuration"]
265pub mod rx_filt;
266#[doc = "STATUS (r) register accessor: UART status register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
267pub type STATUS = crate::Reg<status::STATUS_SPEC>;
268#[doc = "UART status register"]
269pub mod status;
270#[doc = "CONF0 (rw) register accessor: a\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"]
271pub type CONF0 = crate::Reg<conf0::CONF0_SPEC>;
272#[doc = "a"]
273pub mod conf0;
274#[doc = "CONF1 (rw) register accessor: Configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"]
275pub type CONF1 = crate::Reg<conf1::CONF1_SPEC>;
276#[doc = "Configuration register 1"]
277pub mod conf1;
278#[doc = "HWFC_CONF (rw) register accessor: Hardware flow-control configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hwfc_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hwfc_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hwfc_conf`] module"]
279pub type HWFC_CONF = crate::Reg<hwfc_conf::HWFC_CONF_SPEC>;
280#[doc = "Hardware flow-control configuration"]
281pub mod hwfc_conf;
282#[doc = "SLEEP_CONF0 (rw) register accessor: UART sleep configure register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf0`] module"]
283pub type SLEEP_CONF0 = crate::Reg<sleep_conf0::SLEEP_CONF0_SPEC>;
284#[doc = "UART sleep configure register 0"]
285pub mod sleep_conf0;
286#[doc = "SLEEP_CONF1 (rw) register accessor: UART sleep configure register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf1`] module"]
287pub type SLEEP_CONF1 = crate::Reg<sleep_conf1::SLEEP_CONF1_SPEC>;
288#[doc = "UART sleep configure register 1"]
289pub mod sleep_conf1;
290#[doc = "SLEEP_CONF2 (rw) register accessor: UART sleep configure register 2\n\nYou can [`read`](crate::Reg::read) this register and get [`sleep_conf2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sleep_conf2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sleep_conf2`] module"]
291pub type SLEEP_CONF2 = crate::Reg<sleep_conf2::SLEEP_CONF2_SPEC>;
292#[doc = "UART sleep configure register 2"]
293pub mod sleep_conf2;
294#[doc = "SWFC_CONF0 (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`swfc_conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swfc_conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf0`] module"]
295pub type SWFC_CONF0 = crate::Reg<swfc_conf0::SWFC_CONF0_SPEC>;
296#[doc = "Software flow-control character configuration"]
297pub mod swfc_conf0;
298#[doc = "SWFC_CONF1 (rw) register accessor: Software flow-control character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`swfc_conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`swfc_conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@swfc_conf1`] module"]
299pub type SWFC_CONF1 = crate::Reg<swfc_conf1::SWFC_CONF1_SPEC>;
300#[doc = "Software flow-control character configuration"]
301pub mod swfc_conf1;
302#[doc = "TXBRK_CONF (rw) register accessor: Tx Break character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`txbrk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txbrk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txbrk_conf`] module"]
303pub type TXBRK_CONF = crate::Reg<txbrk_conf::TXBRK_CONF_SPEC>;
304#[doc = "Tx Break character configuration"]
305pub mod txbrk_conf;
306#[doc = "IDLE_CONF (rw) register accessor: Frame-end idle configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`idle_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`idle_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@idle_conf`] module"]
307pub type IDLE_CONF = crate::Reg<idle_conf::IDLE_CONF_SPEC>;
308#[doc = "Frame-end idle configuration"]
309pub mod idle_conf;
310#[doc = "RS485_CONF (rw) register accessor: RS485 mode configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rs485_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rs485_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rs485_conf`] module"]
311pub type RS485_CONF = crate::Reg<rs485_conf::RS485_CONF_SPEC>;
312#[doc = "RS485 mode configuration"]
313pub mod rs485_conf;
314#[doc = "AT_CMD_PRECNT (rw) register accessor: Pre-sequence timing configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_precnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_precnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_precnt`] module"]
315pub type AT_CMD_PRECNT = crate::Reg<at_cmd_precnt::AT_CMD_PRECNT_SPEC>;
316#[doc = "Pre-sequence timing configuration"]
317pub mod at_cmd_precnt;
318#[doc = "AT_CMD_POSTCNT (rw) register accessor: Post-sequence timing configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_postcnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_postcnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_postcnt`] module"]
319pub type AT_CMD_POSTCNT = crate::Reg<at_cmd_postcnt::AT_CMD_POSTCNT_SPEC>;
320#[doc = "Post-sequence timing configuration"]
321pub mod at_cmd_postcnt;
322#[doc = "AT_CMD_GAPTOUT (rw) register accessor: Timeout configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_gaptout::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_gaptout::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_gaptout`] module"]
323pub type AT_CMD_GAPTOUT = crate::Reg<at_cmd_gaptout::AT_CMD_GAPTOUT_SPEC>;
324#[doc = "Timeout configuration"]
325pub mod at_cmd_gaptout;
326#[doc = "AT_CMD_CHAR (rw) register accessor: AT escape sequence detection configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`at_cmd_char::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`at_cmd_char::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@at_cmd_char`] module"]
327pub type AT_CMD_CHAR = crate::Reg<at_cmd_char::AT_CMD_CHAR_SPEC>;
328#[doc = "AT escape sequence detection configuration"]
329pub mod at_cmd_char;
330#[doc = "MEM_CONF (rw) register accessor: UART memory power configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mem_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_conf`] module"]
331pub type MEM_CONF = crate::Reg<mem_conf::MEM_CONF_SPEC>;
332#[doc = "UART memory power configuration"]
333pub mod mem_conf;
334#[doc = "TOUT_CONF (rw) register accessor: UART threshold and allocation configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`tout_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tout_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tout_conf`] module"]
335pub type TOUT_CONF = crate::Reg<tout_conf::TOUT_CONF_SPEC>;
336#[doc = "UART threshold and allocation configuration"]
337pub mod tout_conf;
338#[doc = "MEM_TX_STATUS (r) register accessor: Tx-SRAM write and read offset address.\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_tx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_tx_status`] module"]
339pub type MEM_TX_STATUS = crate::Reg<mem_tx_status::MEM_TX_STATUS_SPEC>;
340#[doc = "Tx-SRAM write and read offset address."]
341pub mod mem_tx_status;
342#[doc = "MEM_RX_STATUS (r) register accessor: Rx-SRAM write and read offset address.\n\nYou can [`read`](crate::Reg::read) this register and get [`mem_rx_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mem_rx_status`] module"]
343pub type MEM_RX_STATUS = crate::Reg<mem_rx_status::MEM_RX_STATUS_SPEC>;
344#[doc = "Rx-SRAM write and read offset address."]
345pub mod mem_rx_status;
346#[doc = "FSM_STATUS (r) register accessor: UART transmit and receive status.\n\nYou can [`read`](crate::Reg::read) this register and get [`fsm_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fsm_status`] module"]
347pub type FSM_STATUS = crate::Reg<fsm_status::FSM_STATUS_SPEC>;
348#[doc = "UART transmit and receive status."]
349pub mod fsm_status;
350#[doc = "POSPULSE (r) register accessor: Autobaud high pulse register\n\nYou can [`read`](crate::Reg::read) this register and get [`pospulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pospulse`] module"]
351pub type POSPULSE = crate::Reg<pospulse::POSPULSE_SPEC>;
352#[doc = "Autobaud high pulse register"]
353pub mod pospulse;
354#[doc = "NEGPULSE (r) register accessor: Autobaud low pulse register\n\nYou can [`read`](crate::Reg::read) this register and get [`negpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@negpulse`] module"]
355pub type NEGPULSE = crate::Reg<negpulse::NEGPULSE_SPEC>;
356#[doc = "Autobaud low pulse register"]
357pub mod negpulse;
358#[doc = "LOWPULSE (r) register accessor: Autobaud minimum low pulse duration register\n\nYou can [`read`](crate::Reg::read) this register and get [`lowpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lowpulse`] module"]
359pub type LOWPULSE = crate::Reg<lowpulse::LOWPULSE_SPEC>;
360#[doc = "Autobaud minimum low pulse duration register"]
361pub mod lowpulse;
362#[doc = "HIGHPULSE (r) register accessor: Autobaud minimum high pulse duration register\n\nYou can [`read`](crate::Reg::read) this register and get [`highpulse::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@highpulse`] module"]
363pub type HIGHPULSE = crate::Reg<highpulse::HIGHPULSE_SPEC>;
364#[doc = "Autobaud minimum high pulse duration register"]
365pub mod highpulse;
366#[doc = "RXD_CNT (r) register accessor: Autobaud edge change count register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxd_cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxd_cnt`] module"]
367pub type RXD_CNT = crate::Reg<rxd_cnt::RXD_CNT_SPEC>;
368#[doc = "Autobaud edge change count register"]
369pub mod rxd_cnt;
370#[doc = "CLK_CONF (rw) register accessor: UART core clock configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_conf`] module"]
371pub type CLK_CONF = crate::Reg<clk_conf::CLK_CONF_SPEC>;
372#[doc = "UART core clock configuration"]
373pub mod clk_conf;
374#[doc = "DATE (rw) register accessor: UART Version register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
375pub type DATE = crate::Reg<date::DATE_SPEC>;
376#[doc = "UART Version register"]
377pub mod date;
378#[doc = "AFIFO_STATUS (r) register accessor: UART AFIFO Status\n\nYou can [`read`](crate::Reg::read) this register and get [`afifo_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@afifo_status`] module"]
379pub type AFIFO_STATUS = crate::Reg<afifo_status::AFIFO_STATUS_SPEC>;
380#[doc = "UART AFIFO Status"]
381pub mod afifo_status;
382#[doc = "REG_UPDATE (rw) register accessor: UART Registers Configuration Update register\n\nYou can [`read`](crate::Reg::read) this register and get [`reg_update::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reg_update::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reg_update`] module"]
383pub type REG_UPDATE = crate::Reg<reg_update::REG_UPDATE_SPEC>;
384#[doc = "UART Registers Configuration Update register"]
385pub mod reg_update;
386#[doc = "ID (rw) register accessor: UART ID register\n\nYou can [`read`](crate::Reg::read) this register and get [`id::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`id::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@id`] module"]
387pub type ID = crate::Reg<id::ID_SPEC>;
388#[doc = "UART ID register"]
389pub mod id;