1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `FILTER_THRES` reader - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
6pub type FILTER_THRES_R = crate::FieldReader<u16>;
7#[doc = "Field `FILTER_THRES` writer - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
8pub type FILTER_THRES_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
9#[doc = "Field `FILTER_EN` reader - This is the enable bit for unit %s's input filter."]
10pub type FILTER_EN_R = crate::BitReader;
11#[doc = "Field `FILTER_EN` writer - This is the enable bit for unit %s's input filter."]
12pub type FILTER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `THR_ZERO_EN` reader - This is the enable bit for unit %s's zero comparator."]
14pub type THR_ZERO_EN_R = crate::BitReader;
15#[doc = "Field `THR_ZERO_EN` writer - This is the enable bit for unit %s's zero comparator."]
16pub type THR_ZERO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `THR_H_LIM_EN` reader - This is the enable bit for unit %s's thr_h_lim comparator."]
18pub type THR_H_LIM_EN_R = crate::BitReader;
19#[doc = "Field `THR_H_LIM_EN` writer - This is the enable bit for unit %s's thr_h_lim comparator."]
20pub type THR_H_LIM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `THR_L_LIM_EN` reader - This is the enable bit for unit %s's thr_l_lim comparator."]
22pub type THR_L_LIM_EN_R = crate::BitReader;
23#[doc = "Field `THR_L_LIM_EN` writer - This is the enable bit for unit %s's thr_l_lim comparator."]
24pub type THR_L_LIM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `THR_THRES0_EN` reader - This is the enable bit for unit %s's thres0 comparator."]
26pub type THR_THRES0_EN_R = crate::BitReader;
27#[doc = "Field `THR_THRES0_EN` writer - This is the enable bit for unit %s's thres0 comparator."]
28pub type THR_THRES0_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `THR_THRES1_EN` reader - This is the enable bit for unit %s's thres1 comparator."]
30pub type THR_THRES1_EN_R = crate::BitReader;
31#[doc = "Field `THR_THRES1_EN` writer - This is the enable bit for unit %s's thres1 comparator."]
32pub type THR_THRES1_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Configures the behavior when the signal input of channel %s detects a negative edge.\n\nValue on reset: 0"]
34#[cfg_attr(feature = "defmt", derive(defmt::Format))]
35#[derive(Clone, Copy, Debug, PartialEq, Eq)]
36#[repr(u8)]
37pub enum EDGE_MODE {
38 #[doc = "1: Increase the counter"]
39 Increment = 1,
40 #[doc = "2: Decrease the counter"]
41 Decrement = 2,
42 #[doc = "0: No effect on counter"]
43 Hold = 0,
44}
45impl From<EDGE_MODE> for u8 {
46 #[inline(always)]
47 fn from(variant: EDGE_MODE) -> Self {
48 variant as _
49 }
50}
51impl crate::FieldSpec for EDGE_MODE {
52 type Ux = u8;
53}
54impl crate::IsEnum for EDGE_MODE {}
55#[doc = "Field `CH_NEG_MODE(0-1)` reader - Configures the behavior when the signal input of channel %s detects a negative edge."]
56pub type CH_NEG_MODE_R = crate::FieldReader<EDGE_MODE>;
57impl CH_NEG_MODE_R {
58 #[doc = "Get enumerated values variant"]
59 #[inline(always)]
60 pub const fn variant(&self) -> EDGE_MODE {
61 match self.bits {
62 1 => EDGE_MODE::Increment,
63 2 => EDGE_MODE::Decrement,
64 _ => EDGE_MODE::Hold,
65 }
66 }
67 #[doc = "Increase the counter"]
68 #[inline(always)]
69 pub fn is_increment(&self) -> bool {
70 *self == EDGE_MODE::Increment
71 }
72 #[doc = "Decrease the counter"]
73 #[inline(always)]
74 pub fn is_decrement(&self) -> bool {
75 *self == EDGE_MODE::Decrement
76 }
77 #[doc = "No effect on counter"]
78 #[inline(always)]
79 pub fn is_hold(&self) -> bool {
80 matches!(self.variant(), EDGE_MODE::Hold)
81 }
82}
83#[doc = "Field `CH_NEG_MODE(0-1)` writer - Configures the behavior when the signal input of channel %s detects a negative edge."]
84pub type CH_NEG_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EDGE_MODE, crate::Safe>;
85impl<'a, REG> CH_NEG_MODE_W<'a, REG>
86where
87 REG: crate::Writable + crate::RegisterSpec,
88 REG::Ux: From<u8>,
89{
90 #[doc = "Increase the counter"]
91 #[inline(always)]
92 pub fn increment(self) -> &'a mut crate::W<REG> {
93 self.variant(EDGE_MODE::Increment)
94 }
95 #[doc = "Decrease the counter"]
96 #[inline(always)]
97 pub fn decrement(self) -> &'a mut crate::W<REG> {
98 self.variant(EDGE_MODE::Decrement)
99 }
100 #[doc = "No effect on counter"]
101 #[inline(always)]
102 pub fn hold(self) -> &'a mut crate::W<REG> {
103 self.variant(EDGE_MODE::Hold)
104 }
105}
106#[doc = "Field `CH_POS_MODE(0-1)` reader - Configures the behavior when the signal input of channel %s detects a positive edge."]
107pub use CH_NEG_MODE_R as CH_POS_MODE_R;
108#[doc = "Field `CH_POS_MODE(0-1)` writer - Configures the behavior when the signal input of channel %s detects a positive edge."]
109pub use CH_NEG_MODE_W as CH_POS_MODE_W;
110#[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high.\n\nValue on reset: 0"]
111#[cfg_attr(feature = "defmt", derive(defmt::Format))]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum CTRL_MODE {
115 #[doc = "0: No modification"]
116 Keep = 0,
117 #[doc = "1: Invert behavior (increase -> decrease"]
118 Reverse = 1,
119 #[doc = "2: Inhibit counter modification"]
120 Disable = 2,
121}
122impl From<CTRL_MODE> for u8 {
123 #[inline(always)]
124 fn from(variant: CTRL_MODE) -> Self {
125 variant as _
126 }
127}
128impl crate::FieldSpec for CTRL_MODE {
129 type Ux = u8;
130}
131impl crate::IsEnum for CTRL_MODE {}
132#[doc = "Field `CH_HCTRL_MODE(0-1)` reader - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
133pub type CH_HCTRL_MODE_R = crate::FieldReader<CTRL_MODE>;
134impl CH_HCTRL_MODE_R {
135 #[doc = "Get enumerated values variant"]
136 #[inline(always)]
137 pub const fn variant(&self) -> CTRL_MODE {
138 match self.bits {
139 0 => CTRL_MODE::Keep,
140 1 => CTRL_MODE::Reverse,
141 _ => CTRL_MODE::Disable,
142 }
143 }
144 #[doc = "No modification"]
145 #[inline(always)]
146 pub fn is_keep(&self) -> bool {
147 *self == CTRL_MODE::Keep
148 }
149 #[doc = "Invert behavior (increase -> decrease"]
150 #[inline(always)]
151 pub fn is_reverse(&self) -> bool {
152 *self == CTRL_MODE::Reverse
153 }
154 #[doc = "Inhibit counter modification"]
155 #[inline(always)]
156 pub fn is_disable(&self) -> bool {
157 matches!(self.variant(), CTRL_MODE::Disable)
158 }
159}
160#[doc = "Field `CH_HCTRL_MODE(0-1)` writer - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
161pub type CH_HCTRL_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CTRL_MODE, crate::Safe>;
162impl<'a, REG> CH_HCTRL_MODE_W<'a, REG>
163where
164 REG: crate::Writable + crate::RegisterSpec,
165 REG::Ux: From<u8>,
166{
167 #[doc = "No modification"]
168 #[inline(always)]
169 pub fn keep(self) -> &'a mut crate::W<REG> {
170 self.variant(CTRL_MODE::Keep)
171 }
172 #[doc = "Invert behavior (increase -> decrease"]
173 #[inline(always)]
174 pub fn reverse(self) -> &'a mut crate::W<REG> {
175 self.variant(CTRL_MODE::Reverse)
176 }
177 #[doc = "Inhibit counter modification"]
178 #[inline(always)]
179 pub fn disable(self) -> &'a mut crate::W<REG> {
180 self.variant(CTRL_MODE::Disable)
181 }
182}
183#[doc = "Field `CH_LCTRL_MODE(0-1)` reader - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
184pub use CH_HCTRL_MODE_R as CH_LCTRL_MODE_R;
185#[doc = "Field `CH_LCTRL_MODE(0-1)` writer - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
186pub use CH_HCTRL_MODE_W as CH_LCTRL_MODE_W;
187impl R {
188 #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
189 #[inline(always)]
190 pub fn filter_thres(&self) -> FILTER_THRES_R {
191 FILTER_THRES_R::new((self.bits & 0x03ff) as u16)
192 }
193 #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
194 #[inline(always)]
195 pub fn filter_en(&self) -> FILTER_EN_R {
196 FILTER_EN_R::new(((self.bits >> 10) & 1) != 0)
197 }
198 #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
199 #[inline(always)]
200 pub fn thr_zero_en(&self) -> THR_ZERO_EN_R {
201 THR_ZERO_EN_R::new(((self.bits >> 11) & 1) != 0)
202 }
203 #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
204 #[inline(always)]
205 pub fn thr_h_lim_en(&self) -> THR_H_LIM_EN_R {
206 THR_H_LIM_EN_R::new(((self.bits >> 12) & 1) != 0)
207 }
208 #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
209 #[inline(always)]
210 pub fn thr_l_lim_en(&self) -> THR_L_LIM_EN_R {
211 THR_L_LIM_EN_R::new(((self.bits >> 13) & 1) != 0)
212 }
213 #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
214 #[inline(always)]
215 pub fn thr_thres0_en(&self) -> THR_THRES0_EN_R {
216 THR_THRES0_EN_R::new(((self.bits >> 14) & 1) != 0)
217 }
218 #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
219 #[inline(always)]
220 pub fn thr_thres1_en(&self) -> THR_THRES1_EN_R {
221 THR_THRES1_EN_R::new(((self.bits >> 15) & 1) != 0)
222 }
223 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
224 #[doc = ""]
225 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
226 #[inline(always)]
227 pub fn ch_neg_mode(&self, n: u8) -> CH_NEG_MODE_R {
228 #[allow(clippy::no_effect)]
229 [(); 2][n as usize];
230 CH_NEG_MODE_R::new(((self.bits >> (n * 8 + 16)) & 3) as u8)
231 }
232 #[doc = "Iterator for array of:"]
233 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
234 #[inline(always)]
235 pub fn ch_neg_mode_iter(&self) -> impl Iterator<Item = CH_NEG_MODE_R> + '_ {
236 (0..2).map(move |n| CH_NEG_MODE_R::new(((self.bits >> (n * 8 + 16)) & 3) as u8))
237 }
238 #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
239 #[inline(always)]
240 pub fn ch0_neg_mode(&self) -> CH_NEG_MODE_R {
241 CH_NEG_MODE_R::new(((self.bits >> 16) & 3) as u8)
242 }
243 #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
244 #[inline(always)]
245 pub fn ch1_neg_mode(&self) -> CH_NEG_MODE_R {
246 CH_NEG_MODE_R::new(((self.bits >> 24) & 3) as u8)
247 }
248 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
249 #[doc = ""]
250 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
251 #[inline(always)]
252 pub fn ch_pos_mode(&self, n: u8) -> CH_POS_MODE_R {
253 #[allow(clippy::no_effect)]
254 [(); 2][n as usize];
255 CH_POS_MODE_R::new(((self.bits >> (n * 8 + 18)) & 3) as u8)
256 }
257 #[doc = "Iterator for array of:"]
258 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
259 #[inline(always)]
260 pub fn ch_pos_mode_iter(&self) -> impl Iterator<Item = CH_POS_MODE_R> + '_ {
261 (0..2).map(move |n| CH_POS_MODE_R::new(((self.bits >> (n * 8 + 18)) & 3) as u8))
262 }
263 #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
264 #[inline(always)]
265 pub fn ch0_pos_mode(&self) -> CH_POS_MODE_R {
266 CH_POS_MODE_R::new(((self.bits >> 18) & 3) as u8)
267 }
268 #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
269 #[inline(always)]
270 pub fn ch1_pos_mode(&self) -> CH_POS_MODE_R {
271 CH_POS_MODE_R::new(((self.bits >> 26) & 3) as u8)
272 }
273 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
274 #[doc = ""]
275 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
276 #[inline(always)]
277 pub fn ch_hctrl_mode(&self, n: u8) -> CH_HCTRL_MODE_R {
278 #[allow(clippy::no_effect)]
279 [(); 2][n as usize];
280 CH_HCTRL_MODE_R::new(((self.bits >> (n * 8 + 20)) & 3) as u8)
281 }
282 #[doc = "Iterator for array of:"]
283 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
284 #[inline(always)]
285 pub fn ch_hctrl_mode_iter(&self) -> impl Iterator<Item = CH_HCTRL_MODE_R> + '_ {
286 (0..2).map(move |n| CH_HCTRL_MODE_R::new(((self.bits >> (n * 8 + 20)) & 3) as u8))
287 }
288 #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
289 #[inline(always)]
290 pub fn ch0_hctrl_mode(&self) -> CH_HCTRL_MODE_R {
291 CH_HCTRL_MODE_R::new(((self.bits >> 20) & 3) as u8)
292 }
293 #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
294 #[inline(always)]
295 pub fn ch1_hctrl_mode(&self) -> CH_HCTRL_MODE_R {
296 CH_HCTRL_MODE_R::new(((self.bits >> 28) & 3) as u8)
297 }
298 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
299 #[doc = ""]
300 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
301 #[inline(always)]
302 pub fn ch_lctrl_mode(&self, n: u8) -> CH_LCTRL_MODE_R {
303 #[allow(clippy::no_effect)]
304 [(); 2][n as usize];
305 CH_LCTRL_MODE_R::new(((self.bits >> (n * 8 + 22)) & 3) as u8)
306 }
307 #[doc = "Iterator for array of:"]
308 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
309 #[inline(always)]
310 pub fn ch_lctrl_mode_iter(&self) -> impl Iterator<Item = CH_LCTRL_MODE_R> + '_ {
311 (0..2).map(move |n| CH_LCTRL_MODE_R::new(((self.bits >> (n * 8 + 22)) & 3) as u8))
312 }
313 #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
314 #[inline(always)]
315 pub fn ch0_lctrl_mode(&self) -> CH_LCTRL_MODE_R {
316 CH_LCTRL_MODE_R::new(((self.bits >> 22) & 3) as u8)
317 }
318 #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
319 #[inline(always)]
320 pub fn ch1_lctrl_mode(&self) -> CH_LCTRL_MODE_R {
321 CH_LCTRL_MODE_R::new(((self.bits >> 30) & 3) as u8)
322 }
323}
324#[cfg(feature = "impl-register-debug")]
325impl core::fmt::Debug for R {
326 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
327 f.debug_struct("CONF0")
328 .field("filter_thres", &self.filter_thres())
329 .field("filter_en", &self.filter_en())
330 .field("thr_zero_en", &self.thr_zero_en())
331 .field("thr_h_lim_en", &self.thr_h_lim_en())
332 .field("thr_l_lim_en", &self.thr_l_lim_en())
333 .field("thr_thres0_en", &self.thr_thres0_en())
334 .field("thr_thres1_en", &self.thr_thres1_en())
335 .field("ch0_neg_mode", &self.ch0_neg_mode())
336 .field("ch1_neg_mode", &self.ch1_neg_mode())
337 .field("ch0_pos_mode", &self.ch0_pos_mode())
338 .field("ch1_pos_mode", &self.ch1_pos_mode())
339 .field("ch0_hctrl_mode", &self.ch0_hctrl_mode())
340 .field("ch1_hctrl_mode", &self.ch1_hctrl_mode())
341 .field("ch0_lctrl_mode", &self.ch0_lctrl_mode())
342 .field("ch1_lctrl_mode", &self.ch1_lctrl_mode())
343 .finish()
344 }
345}
346impl W {
347 #[doc = "Bits 0:9 - This sets the maximum threshold, in APB_CLK cycles, for the filter. Any pulses with width less than this will be ignored when the filter is enabled."]
348 #[inline(always)]
349 pub fn filter_thres(&mut self) -> FILTER_THRES_W<CONF0_SPEC> {
350 FILTER_THRES_W::new(self, 0)
351 }
352 #[doc = "Bit 10 - This is the enable bit for unit %s's input filter."]
353 #[inline(always)]
354 pub fn filter_en(&mut self) -> FILTER_EN_W<CONF0_SPEC> {
355 FILTER_EN_W::new(self, 10)
356 }
357 #[doc = "Bit 11 - This is the enable bit for unit %s's zero comparator."]
358 #[inline(always)]
359 pub fn thr_zero_en(&mut self) -> THR_ZERO_EN_W<CONF0_SPEC> {
360 THR_ZERO_EN_W::new(self, 11)
361 }
362 #[doc = "Bit 12 - This is the enable bit for unit %s's thr_h_lim comparator."]
363 #[inline(always)]
364 pub fn thr_h_lim_en(&mut self) -> THR_H_LIM_EN_W<CONF0_SPEC> {
365 THR_H_LIM_EN_W::new(self, 12)
366 }
367 #[doc = "Bit 13 - This is the enable bit for unit %s's thr_l_lim comparator."]
368 #[inline(always)]
369 pub fn thr_l_lim_en(&mut self) -> THR_L_LIM_EN_W<CONF0_SPEC> {
370 THR_L_LIM_EN_W::new(self, 13)
371 }
372 #[doc = "Bit 14 - This is the enable bit for unit %s's thres0 comparator."]
373 #[inline(always)]
374 pub fn thr_thres0_en(&mut self) -> THR_THRES0_EN_W<CONF0_SPEC> {
375 THR_THRES0_EN_W::new(self, 14)
376 }
377 #[doc = "Bit 15 - This is the enable bit for unit %s's thres1 comparator."]
378 #[inline(always)]
379 pub fn thr_thres1_en(&mut self) -> THR_THRES1_EN_W<CONF0_SPEC> {
380 THR_THRES1_EN_W::new(self, 15)
381 }
382 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a negative edge."]
383 #[doc = ""]
384 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_NEG_MODE` field.</div>"]
385 #[inline(always)]
386 pub fn ch_neg_mode(&mut self, n: u8) -> CH_NEG_MODE_W<CONF0_SPEC> {
387 #[allow(clippy::no_effect)]
388 [(); 2][n as usize];
389 CH_NEG_MODE_W::new(self, n * 8 + 16)
390 }
391 #[doc = "Bits 16:17 - Configures the behavior when the signal input of channel 0 detects a negative edge."]
392 #[inline(always)]
393 pub fn ch0_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
394 CH_NEG_MODE_W::new(self, 16)
395 }
396 #[doc = "Bits 24:25 - Configures the behavior when the signal input of channel 1 detects a negative edge."]
397 #[inline(always)]
398 pub fn ch1_neg_mode(&mut self) -> CH_NEG_MODE_W<CONF0_SPEC> {
399 CH_NEG_MODE_W::new(self, 24)
400 }
401 #[doc = "Configures the behavior when the signal input of channel (0-1) detects a positive edge."]
402 #[doc = ""]
403 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_POS_MODE` field.</div>"]
404 #[inline(always)]
405 pub fn ch_pos_mode(&mut self, n: u8) -> CH_POS_MODE_W<CONF0_SPEC> {
406 #[allow(clippy::no_effect)]
407 [(); 2][n as usize];
408 CH_POS_MODE_W::new(self, n * 8 + 18)
409 }
410 #[doc = "Bits 18:19 - Configures the behavior when the signal input of channel 0 detects a positive edge."]
411 #[inline(always)]
412 pub fn ch0_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
413 CH_POS_MODE_W::new(self, 18)
414 }
415 #[doc = "Bits 26:27 - Configures the behavior when the signal input of channel 1 detects a positive edge."]
416 #[inline(always)]
417 pub fn ch1_pos_mode(&mut self) -> CH_POS_MODE_W<CONF0_SPEC> {
418 CH_POS_MODE_W::new(self, 26)
419 }
420 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
421 #[doc = ""]
422 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_HCTRL_MODE` field.</div>"]
423 #[inline(always)]
424 pub fn ch_hctrl_mode(&mut self, n: u8) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
425 #[allow(clippy::no_effect)]
426 [(); 2][n as usize];
427 CH_HCTRL_MODE_W::new(self, n * 8 + 20)
428 }
429 #[doc = "Bits 20:21 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
430 #[inline(always)]
431 pub fn ch0_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
432 CH_HCTRL_MODE_W::new(self, 20)
433 }
434 #[doc = "Bits 28:29 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is high."]
435 #[inline(always)]
436 pub fn ch1_hctrl_mode(&mut self) -> CH_HCTRL_MODE_W<CONF0_SPEC> {
437 CH_HCTRL_MODE_W::new(self, 28)
438 }
439 #[doc = "Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
440 #[doc = ""]
441 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_LCTRL_MODE` field.</div>"]
442 #[inline(always)]
443 pub fn ch_lctrl_mode(&mut self, n: u8) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
444 #[allow(clippy::no_effect)]
445 [(); 2][n as usize];
446 CH_LCTRL_MODE_W::new(self, n * 8 + 22)
447 }
448 #[doc = "Bits 22:23 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
449 #[inline(always)]
450 pub fn ch0_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
451 CH_LCTRL_MODE_W::new(self, 22)
452 }
453 #[doc = "Bits 30:31 - Configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be modified when the control signal is low."]
454 #[inline(always)]
455 pub fn ch1_lctrl_mode(&mut self) -> CH_LCTRL_MODE_W<CONF0_SPEC> {
456 CH_LCTRL_MODE_W::new(self, 30)
457 }
458}
459#[doc = "Configuration register 0 for unit\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
460pub struct CONF0_SPEC;
461impl crate::RegisterSpec for CONF0_SPEC {
462 type Ux = u32;
463}
464#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
465impl crate::Readable for CONF0_SPEC {}
466#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
467impl crate::Writable for CONF0_SPEC {
468 type Safety = crate::Unsafe;
469}
470#[doc = "`reset()` method sets CONF0 to value 0x3c10"]
471impl crate::Resettable for CONF0_SPEC {
472 const RESET_VALUE: u32 = 0x3c10;
473}