esp32c6/parl_io/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `TX_FIFO_REMPTY` reader - Write 1 to enable TX_FIFO_REMPTY_INTR."]
6pub type TX_FIFO_REMPTY_R = crate::BitReader;
7#[doc = "Field `TX_FIFO_REMPTY` writer - Write 1 to enable TX_FIFO_REMPTY_INTR."]
8pub type TX_FIFO_REMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_FIFO_WOVF` reader - Write 1 to enable RX_FIFO_WOVF_INTR."]
10pub type RX_FIFO_WOVF_R = crate::BitReader;
11#[doc = "Field `RX_FIFO_WOVF` writer - Write 1 to enable RX_FIFO_WOVF_INTR."]
12pub type RX_FIFO_WOVF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TX_EOF` reader - Write 1 to enable TX_EOF_INTR."]
14pub type TX_EOF_R = crate::BitReader;
15#[doc = "Field `TX_EOF` writer - Write 1 to enable TX_EOF_INTR."]
16pub type TX_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - Write 1 to enable TX_FIFO_REMPTY_INTR."]
19    #[inline(always)]
20    pub fn tx_fifo_rempty(&self) -> TX_FIFO_REMPTY_R {
21        TX_FIFO_REMPTY_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - Write 1 to enable RX_FIFO_WOVF_INTR."]
24    #[inline(always)]
25    pub fn rx_fifo_wovf(&self) -> RX_FIFO_WOVF_R {
26        RX_FIFO_WOVF_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Write 1 to enable TX_EOF_INTR."]
29    #[inline(always)]
30    pub fn tx_eof(&self) -> TX_EOF_R {
31        TX_EOF_R::new(((self.bits >> 2) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("INT_ENA")
38            .field("tx_fifo_rempty", &self.tx_fifo_rempty())
39            .field("rx_fifo_wovf", &self.rx_fifo_wovf())
40            .field("tx_eof", &self.tx_eof())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Write 1 to enable TX_FIFO_REMPTY_INTR."]
46    #[inline(always)]
47    pub fn tx_fifo_rempty(&mut self) -> TX_FIFO_REMPTY_W<INT_ENA_SPEC> {
48        TX_FIFO_REMPTY_W::new(self, 0)
49    }
50    #[doc = "Bit 1 - Write 1 to enable RX_FIFO_WOVF_INTR."]
51    #[inline(always)]
52    pub fn rx_fifo_wovf(&mut self) -> RX_FIFO_WOVF_W<INT_ENA_SPEC> {
53        RX_FIFO_WOVF_W::new(self, 1)
54    }
55    #[doc = "Bit 2 - Write 1 to enable TX_EOF_INTR."]
56    #[inline(always)]
57    pub fn tx_eof(&mut self) -> TX_EOF_W<INT_ENA_SPEC> {
58        TX_EOF_W::new(self, 2)
59    }
60}
61#[doc = "Parallel IO interrupt enable singal configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct INT_ENA_SPEC;
63impl crate::RegisterSpec for INT_ENA_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
67impl crate::Readable for INT_ENA_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
69impl crate::Writable for INT_ENA_SPEC {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets INT_ENA to value 0"]
73impl crate::Resettable for INT_ENA_SPEC {}
esp32c6/parl_io/int_ena.rs

esp32c6/parl_io/
int_ena.rs
