esp32c6/mcpwm0/timer/
sync.rs

1#[doc = "Register `SYNC` reader"]
2pub type R = crate::R<SYNC_SPEC>;
3#[doc = "Register `SYNC` writer"]
4pub type W = crate::W<SYNC_SPEC>;
5#[doc = "Field `SYNCI_EN` reader - When set, timer reloading with phase on sync input event is enabled."]
6pub type SYNCI_EN_R = crate::BitReader;
7#[doc = "Field `SYNCI_EN` writer - When set, timer reloading with phase on sync input event is enabled."]
8pub type SYNCI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SW` reader - Toggling this bit will trigger a software sync."]
10pub type SW_R = crate::BitReader;
11#[doc = "Field `SW` writer - Toggling this bit will trigger a software sync."]
12pub type SW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SYNCO_SEL` reader - PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit"]
14pub type SYNCO_SEL_R = crate::FieldReader;
15#[doc = "Field `SYNCO_SEL` writer - PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit"]
16pub type SYNCO_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `PHASE` reader - phase for timer reload on sync event"]
18pub type PHASE_R = crate::FieldReader<u16>;
19#[doc = "Field `PHASE` writer - phase for timer reload on sync event"]
20pub type PHASE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
21#[doc = "Field `PHASE_DIRECTION` reader - Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease"]
22pub type PHASE_DIRECTION_R = crate::BitReader;
23#[doc = "Field `PHASE_DIRECTION` writer - Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease"]
24pub type PHASE_DIRECTION_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
27    #[inline(always)]
28    pub fn synci_en(&self) -> SYNCI_EN_R {
29        SYNCI_EN_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - Toggling this bit will trigger a software sync."]
32    #[inline(always)]
33    pub fn sw(&self) -> SW_R {
34        SW_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bits 2:3 - PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit"]
37    #[inline(always)]
38    pub fn synco_sel(&self) -> SYNCO_SEL_R {
39        SYNCO_SEL_R::new(((self.bits >> 2) & 3) as u8)
40    }
41    #[doc = "Bits 4:19 - phase for timer reload on sync event"]
42    #[inline(always)]
43    pub fn phase(&self) -> PHASE_R {
44        PHASE_R::new(((self.bits >> 4) & 0xffff) as u16)
45    }
46    #[doc = "Bit 20 - Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease"]
47    #[inline(always)]
48    pub fn phase_direction(&self) -> PHASE_DIRECTION_R {
49        PHASE_DIRECTION_R::new(((self.bits >> 20) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("SYNC")
56            .field("synci_en", &self.synci_en())
57            .field("sw", &self.sw())
58            .field("synco_sel", &self.synco_sel())
59            .field("phase", &self.phase())
60            .field("phase_direction", &self.phase_direction())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - When set, timer reloading with phase on sync input event is enabled."]
66    #[inline(always)]
67    pub fn synci_en(&mut self) -> SYNCI_EN_W<SYNC_SPEC> {
68        SYNCI_EN_W::new(self, 0)
69    }
70    #[doc = "Bit 1 - Toggling this bit will trigger a software sync."]
71    #[inline(always)]
72    pub fn sw(&mut self) -> SW_W<SYNC_SPEC> {
73        SW_W::new(self, 1)
74    }
75    #[doc = "Bits 2:3 - PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit"]
76    #[inline(always)]
77    pub fn synco_sel(&mut self) -> SYNCO_SEL_W<SYNC_SPEC> {
78        SYNCO_SEL_W::new(self, 2)
79    }
80    #[doc = "Bits 4:19 - phase for timer reload on sync event"]
81    #[inline(always)]
82    pub fn phase(&mut self) -> PHASE_W<SYNC_SPEC> {
83        PHASE_W::new(self, 4)
84    }
85    #[doc = "Bit 20 - Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease"]
86    #[inline(always)]
87    pub fn phase_direction(&mut self) -> PHASE_DIRECTION_W<SYNC_SPEC> {
88        PHASE_DIRECTION_W::new(self, 20)
89    }
90}
91#[doc = "PWM TIMERx sync function configuration register.\n\nYou can [`read`](crate::Reg::read) this register and get [`sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct SYNC_SPEC;
93impl crate::RegisterSpec for SYNC_SPEC {
94    type Ux = u32;
95}
96#[doc = "`read()` method returns [`sync::R`](R) reader structure"]
97impl crate::Readable for SYNC_SPEC {}
98#[doc = "`write(|w| ..)` method takes [`sync::W`](W) writer structure"]
99impl crate::Writable for SYNC_SPEC {
100    type Safety = crate::Unsafe;
101}
102#[doc = "`reset()` method sets SYNC to value 0"]
103impl crate::Resettable for SYNC_SPEC {}
esp32c6/mcpwm0/timer/sync.rs

esp32c6/mcpwm0/timer/
sync.rs
