esp32c6/extmem/
l1_cache_acs_fail_int_clr.rs

1#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` reader"]
2pub type R = crate::R<L1_CACHE_ACS_FAIL_INT_CLR_SPEC>;
3#[doc = "Register `L1_CACHE_ACS_FAIL_INT_CLR` writer"]
4pub type W = crate::W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC>;
5#[doc = "Field `L1_ICACHE0_FAIL_INT_CLR` reader - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
6pub type L1_ICACHE0_FAIL_INT_CLR_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE1_FAIL_INT_CLR` reader - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."]
8pub type L1_ICACHE1_FAIL_INT_CLR_R = crate::BitReader;
9#[doc = "Field `L1_ICACHE2_FAIL_INT_CLR` reader - Reserved"]
10pub type L1_ICACHE2_FAIL_INT_CLR_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE3_FAIL_INT_CLR` reader - Reserved"]
12pub type L1_ICACHE3_FAIL_INT_CLR_R = crate::BitReader;
13#[doc = "Field `L1_CACHE_FAIL_INT_CLR` writer - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
14pub type L1_CACHE_FAIL_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15impl R {
16    #[doc = "Bit 0 - The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0."]
17    #[inline(always)]
18    pub fn l1_icache0_fail_int_clr(&self) -> L1_ICACHE0_FAIL_INT_CLR_R {
19        L1_ICACHE0_FAIL_INT_CLR_R::new((self.bits & 1) != 0)
20    }
21    #[doc = "Bit 1 - The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1."]
22    #[inline(always)]
23    pub fn l1_icache1_fail_int_clr(&self) -> L1_ICACHE1_FAIL_INT_CLR_R {
24        L1_ICACHE1_FAIL_INT_CLR_R::new(((self.bits >> 1) & 1) != 0)
25    }
26    #[doc = "Bit 2 - Reserved"]
27    #[inline(always)]
28    pub fn l1_icache2_fail_int_clr(&self) -> L1_ICACHE2_FAIL_INT_CLR_R {
29        L1_ICACHE2_FAIL_INT_CLR_R::new(((self.bits >> 2) & 1) != 0)
30    }
31    #[doc = "Bit 3 - Reserved"]
32    #[inline(always)]
33    pub fn l1_icache3_fail_int_clr(&self) -> L1_ICACHE3_FAIL_INT_CLR_R {
34        L1_ICACHE3_FAIL_INT_CLR_R::new(((self.bits >> 3) & 1) != 0)
35    }
36}
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for R {
39    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
40        f.debug_struct("L1_CACHE_ACS_FAIL_INT_CLR")
41            .field("l1_icache0_fail_int_clr", &self.l1_icache0_fail_int_clr())
42            .field("l1_icache1_fail_int_clr", &self.l1_icache1_fail_int_clr())
43            .field("l1_icache2_fail_int_clr", &self.l1_icache2_fail_int_clr())
44            .field("l1_icache3_fail_int_clr", &self.l1_icache3_fail_int_clr())
45            .finish()
46    }
47}
48impl W {
49    #[doc = "Bit 4 - The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache."]
50    #[inline(always)]
51    pub fn l1_cache_fail_int_clr(
52        &mut self,
53    ) -> L1_CACHE_FAIL_INT_CLR_W<L1_CACHE_ACS_FAIL_INT_CLR_SPEC> {
54        L1_CACHE_FAIL_INT_CLR_W::new(self, 4)
55    }
56}
57#[doc = "L1-Cache Access Fail Interrupt clear register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_acs_fail_int_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
58pub struct L1_CACHE_ACS_FAIL_INT_CLR_SPEC;
59impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {
60    type Ux = u32;
61}
62#[doc = "`read()` method returns [`l1_cache_acs_fail_int_clr::R`](R) reader structure"]
63impl crate::Readable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {}
64#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_clr::W`](W) writer structure"]
65impl crate::Writable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {
66    type Safety = crate::Unsafe;
67}
68#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_CLR to value 0"]
69impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_CLR_SPEC {}
esp32c6/extmem/l1_cache_acs_fail_int_clr.rs

esp32c6/extmem/
l1_cache_acs_fail_int_clr.rs
