esp32c6/apb_saradc/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `TSENS` writer - saradc tsens interrupt clear"]
4pub type TSENS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `THRES1_LOW` writer - saradc thres1 low interrupt clear"]
6pub type THRES1_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `THRES0_LOW` writer - saradc thres0 low interrupt clear"]
8pub type THRES0_LOW_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `THRES1_HIGH` writer - saradc thres1 high interrupt clear"]
10pub type THRES1_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `THRES0_HIGH` writer - saradc thres0 high interrupt clear"]
12pub type THRES0_HIGH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ADC2_DONE` writer - saradc2 done interrupt clear"]
14pub type ADC2_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `ADC1_DONE` writer - saradc1 done interrupt clear"]
16pub type ADC1_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[cfg(feature = "impl-register-debug")]
18impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
19    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
20        write!(f, "(not readable)")
21    }
22}
23impl W {
24    #[doc = "Bit 25 - saradc tsens interrupt clear"]
25    #[inline(always)]
26    pub fn tsens(&mut self) -> TSENS_W<INT_CLR_SPEC> {
27        TSENS_W::new(self, 25)
28    }
29    #[doc = "Bit 26 - saradc thres1 low interrupt clear"]
30    #[inline(always)]
31    pub fn thres1_low(&mut self) -> THRES1_LOW_W<INT_CLR_SPEC> {
32        THRES1_LOW_W::new(self, 26)
33    }
34    #[doc = "Bit 27 - saradc thres0 low interrupt clear"]
35    #[inline(always)]
36    pub fn thres0_low(&mut self) -> THRES0_LOW_W<INT_CLR_SPEC> {
37        THRES0_LOW_W::new(self, 27)
38    }
39    #[doc = "Bit 28 - saradc thres1 high interrupt clear"]
40    #[inline(always)]
41    pub fn thres1_high(&mut self) -> THRES1_HIGH_W<INT_CLR_SPEC> {
42        THRES1_HIGH_W::new(self, 28)
43    }
44    #[doc = "Bit 29 - saradc thres0 high interrupt clear"]
45    #[inline(always)]
46    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<INT_CLR_SPEC> {
47        THRES0_HIGH_W::new(self, 29)
48    }
49    #[doc = "Bit 30 - saradc2 done interrupt clear"]
50    #[inline(always)]
51    pub fn adc2_done(&mut self) -> ADC2_DONE_W<INT_CLR_SPEC> {
52        ADC2_DONE_W::new(self, 30)
53    }
54    #[doc = "Bit 31 - saradc1 done interrupt clear"]
55    #[inline(always)]
56    pub fn adc1_done(&mut self) -> ADC1_DONE_W<INT_CLR_SPEC> {
57        ADC1_DONE_W::new(self, 31)
58    }
59}
60#[doc = "digital saradc int register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct INT_CLR_SPEC;
62impl crate::RegisterSpec for INT_CLR_SPEC {
63    type Ux = u32;
64}
65#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
66impl crate::Writable for INT_CLR_SPEC {
67    type Safety = crate::Unsafe;
68    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xfe00_0000;
69}
70#[doc = "`reset()` method sets INT_CLR to value 0"]
71impl crate::Resettable for INT_CLR_SPEC {}
esp32c6/apb_saradc/int_clr.rs

esp32c6/apb_saradc/
int_clr.rs
