Module cfg_data7

SDIO configuration register

Structs

CFG_DATA7_SPEC

SDIO configuration register

Type Aliases

CHIP_STATE_R

Field CHIP_STATE reader - configure cis addr 312, 315, 568 and 571

CHIP_STATE_W

Field CHIP_STATE writer - configure cis addr 312, 315, 568 and 571

CLK_EN_R

Field CLK_EN reader - sdio apb clock for configuration force on control:0-gating,1-force on.

CLK_EN_W

Field CLK_EN writer - sdio apb clock for configuration force on control:0-gating,1-force on.

DDR50_BLK_LEN_FIX_EN_R

Field DDR50_BLK_LEN_FIX_EN reader - enable block length to be fixed to 512 bytes in ddr50 mode

DDR50_BLK_LEN_FIX_EN_W

Field DDR50_BLK_LEN_FIX_EN writer - enable block length to be fixed to 512 bytes in ddr50 mode

ESDIO_DATA1_INT_EN_R

Field ESDIO_DATA1_INT_EN reader - enable sdio interrupt on data1 line

ESDIO_DATA1_INT_EN_W

Field ESDIO_DATA1_INT_EN writer - enable sdio interrupt on data1 line

PIN_STATE_R

Field PIN_STATE reader - configure cis addr 318 and 574

PIN_STATE_W

Field PIN_STATE writer - configure cis addr 318 and 574

R

Register CFG_DATA7 reader

SAI_R

Field SAI reader - configure if support asynchronous interrupt in cccr

SAI_W

Field SAI writer - configure if support asynchronous interrupt in cccr

SDDR50_R

Field SDDR50 reader - configure if support sdr50 mode in cccr

SDDR50_W

Field SDDR50 writer - configure if support sdr50 mode in cccr

SDIO_IOREADY0_R

Field SDIO_IOREADY0 reader - sdio io ready, high enable

SDIO_IOREADY0_W

Field SDIO_IOREADY0 writer - sdio io ready, high enable

SDIO_MEM_PD_R

Field SDIO_MEM_PD reader - sdio memory power down, high active

SDIO_MEM_PD_W

Field SDIO_MEM_PD writer - sdio memory power down, high active

SDIO_RST_R

Field SDIO_RST reader - soft reset control for sdio module

SDIO_RST_W

Field SDIO_RST writer - soft reset control for sdio module

SDIO_SWITCH_VOLT_SW_R

Field SDIO_SWITCH_VOLT_SW reader - control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V

SDIO_SWITCH_VOLT_SW_W

Field SDIO_SWITCH_VOLT_SW writer - control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V

SDIO_WAKEUP_CLR_W

Field SDIO_WAKEUP_CLR writer - clear sdio_wake_up signal after the chip wakes up

SDTA_R

Field SDTA reader - configure if support driver type A in cccr

SDTA_W

Field SDTA writer - configure if support driver type A in cccr

SDTC_R

Field SDTC reader - configure if support driver type C in cccr

SDTC_W

Field SDTC writer - configure if support driver type C in cccr

SDTD_R

Field SDTD reader - configure if support driver type D in cccr

SDTD_W

Field SDTD writer - configure if support driver type D in cccr

SSDR50_R

Field SSDR50 reader - configure if support ddr50 mode in cccr

SSDR50_W

Field SSDR50 writer - configure if support ddr50 mode in cccr

SSDR104_R

Field SSDR104 reader - configure if support sdr104 mode in cccr

SSDR104_W

Field SSDR104 writer - configure if support sdr104 mode in cccr

W

Register CFG_DATA7 writer