esp32c6/extmem/
l1_icache0_autoload_ctrl.rs

1#[doc = "Register `L1_ICACHE0_AUTOLOAD_CTRL` reader"]
2pub type R = crate::R<L1_ICACHE0_AUTOLOAD_CTRL_SPEC>;
3#[doc = "Field `L1_ICACHE0_AUTOLOAD_ENA` reader - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."]
4pub type L1_ICACHE0_AUTOLOAD_ENA_R = crate::BitReader;
5#[doc = "Field `L1_ICACHE0_AUTOLOAD_DONE` reader - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."]
6pub type L1_ICACHE0_AUTOLOAD_DONE_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE0_AUTOLOAD_ORDER` reader - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."]
8pub type L1_ICACHE0_AUTOLOAD_ORDER_R = crate::BitReader;
9#[doc = "Field `L1_ICACHE0_AUTOLOAD_TRIGGER_MODE` reader - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."]
10pub type L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R = crate::FieldReader;
11#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT0_ENA` reader - The bit is used to enable the first section for autoload operation on L1-ICache0."]
12pub type L1_ICACHE0_AUTOLOAD_SCT0_ENA_R = crate::BitReader;
13#[doc = "Field `L1_ICACHE0_AUTOLOAD_SCT1_ENA` reader - The bit is used to enable the second section for autoload operation on L1-ICache0."]
14pub type L1_ICACHE0_AUTOLOAD_SCT1_ENA_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE0_AUTOLOAD_RGID` reader - The bit is used to set the gid of l1 icache0 autoload."]
16pub type L1_ICACHE0_AUTOLOAD_RGID_R = crate::FieldReader;
17impl R {
18    #[doc = "Bit 0 - The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable."]
19    #[inline(always)]
20    pub fn l1_icache0_autoload_ena(&self) -> L1_ICACHE0_AUTOLOAD_ENA_R {
21        L1_ICACHE0_AUTOLOAD_ENA_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished."]
24    #[inline(always)]
25    pub fn l1_icache0_autoload_done(&self) -> L1_ICACHE0_AUTOLOAD_DONE_R {
26        L1_ICACHE0_AUTOLOAD_DONE_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending."]
29    #[inline(always)]
30    pub fn l1_icache0_autoload_order(&self) -> L1_ICACHE0_AUTOLOAD_ORDER_R {
31        L1_ICACHE0_AUTOLOAD_ORDER_R::new(((self.bits >> 2) & 1) != 0)
32    }
33    #[doc = "Bits 3:4 - The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger."]
34    #[inline(always)]
35    pub fn l1_icache0_autoload_trigger_mode(&self) -> L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R {
36        L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R::new(((self.bits >> 3) & 3) as u8)
37    }
38    #[doc = "Bit 8 - The bit is used to enable the first section for autoload operation on L1-ICache0."]
39    #[inline(always)]
40    pub fn l1_icache0_autoload_sct0_ena(&self) -> L1_ICACHE0_AUTOLOAD_SCT0_ENA_R {
41        L1_ICACHE0_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0)
42    }
43    #[doc = "Bit 9 - The bit is used to enable the second section for autoload operation on L1-ICache0."]
44    #[inline(always)]
45    pub fn l1_icache0_autoload_sct1_ena(&self) -> L1_ICACHE0_AUTOLOAD_SCT1_ENA_R {
46        L1_ICACHE0_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0)
47    }
48    #[doc = "Bits 10:13 - The bit is used to set the gid of l1 icache0 autoload."]
49    #[inline(always)]
50    pub fn l1_icache0_autoload_rgid(&self) -> L1_ICACHE0_AUTOLOAD_RGID_R {
51        L1_ICACHE0_AUTOLOAD_RGID_R::new(((self.bits >> 10) & 0x0f) as u8)
52    }
53}
54#[cfg(feature = "impl-register-debug")]
55impl core::fmt::Debug for R {
56    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
57        f.debug_struct("L1_ICACHE0_AUTOLOAD_CTRL")
58            .field("l1_icache0_autoload_ena", &self.l1_icache0_autoload_ena())
59            .field("l1_icache0_autoload_done", &self.l1_icache0_autoload_done())
60            .field(
61                "l1_icache0_autoload_order",
62                &self.l1_icache0_autoload_order(),
63            )
64            .field(
65                "l1_icache0_autoload_trigger_mode",
66                &self.l1_icache0_autoload_trigger_mode(),
67            )
68            .field(
69                "l1_icache0_autoload_sct0_ena",
70                &self.l1_icache0_autoload_sct0_ena(),
71            )
72            .field(
73                "l1_icache0_autoload_sct1_ena",
74                &self.l1_icache0_autoload_sct1_ena(),
75            )
76            .field("l1_icache0_autoload_rgid", &self.l1_icache0_autoload_rgid())
77            .finish()
78    }
79}
80#[doc = "L1 instruction Cache 0 autoload-operation control register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_icache0_autoload_ctrl::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
81pub struct L1_ICACHE0_AUTOLOAD_CTRL_SPEC;
82impl crate::RegisterSpec for L1_ICACHE0_AUTOLOAD_CTRL_SPEC {
83    type Ux = u32;
84}
85#[doc = "`read()` method returns [`l1_icache0_autoload_ctrl::R`](R) reader structure"]
86impl crate::Readable for L1_ICACHE0_AUTOLOAD_CTRL_SPEC {}
87#[doc = "`reset()` method sets L1_ICACHE0_AUTOLOAD_CTRL to value 0x02"]
88impl crate::Resettable for L1_ICACHE0_AUTOLOAD_CTRL_SPEC {
89    const RESET_VALUE: u32 = 0x02;
90}
esp32c6/extmem/l1_icache0_autoload_ctrl.rs

esp32c6/extmem/
l1_icache0_autoload_ctrl.rs
