Expand description
SPI (Serial Peripheral Interface) Controller 0
Modules§
- axi_
err_ addr - SPI0 AXI request error address.
- cache_
fctrl - SPI0 bit mode control register.
- cache_
sctrl - SPI0 external RAM control register
- clock
- SPI clock division control register.
- clock_
gate - SPI0 clock gate register
- cmd
- SPI0 FSM status register
- ctrl
- SPI0 control register.
- ctrl1
- SPI0 control1 register.
- ctrl2
- SPI0 control2 register.
- date
- SPI0 version control register
- ddr
- SPI0 flash DDR mode control register
- din_
mode - MSPI flash input timing delay mode control register
- din_num
- MSPI flash input timing delay number control register
- dout_
mode - MSPI flash output timing adjustment control register
- dpa_
ctrl - SPI memory cryption DPA register
- ecc_
ctrl - MSPI ECC control register
- ecc_
err_ addr - MSPI ECC error address register
- fsm
- SPI0 FSM status register
- int_clr
- SPI0 interrupt clear register
- int_ena
- SPI0 interrupt enable register
- int_raw
- SPI0 interrupt raw register
- int_st
- SPI0 interrupt status register
- misc
- SPI0 misc register
- mmu_
item_ content - MSPI-MMU item content register
- mmu_
item_ index - MSPI-MMU item index register
- mmu_
power_ ctrl - MSPI MMU power control register
- pms_
reject - SPI1 access reject register
- rd_
status - SPI0 read control register.
- registerrnd_
eco_ high - MSPI ECO high register
- registerrnd_
eco_ low - MSPI ECO low register
- spi_
fmem_ pms_ addr - SPI1 flash ACE section %s start address register
- spi_
fmem_ pms_ attr - MSPI flash ACE section %s attribute register
- spi_
fmem_ pms_ size - SPI1 flash ACE section %s start address register
- spi_
smem_ ac - MSPI external RAM ECC and SPI CS timing control register
- spi_
smem_ ddr - SPI0 external RAM DDR mode control register
- spi_
smem_ din_ mode - MSPI external RAM input timing delay mode control register
- spi_
smem_ din_ num - MSPI external RAM input timing delay number control register
- spi_
smem_ dout_ mode - MSPI external RAM output timing adjustment control register
- spi_
smem_ ecc_ ctrl - MSPI ECC control register
- spi_
smem_ pms_ addr - SPI1 external RAM ACE section %s start address register
- spi_
smem_ pms_ attr - SPI1 flash ACE section %s start address register
- spi_
smem_ pms_ size - SPI1 external RAM ACE section %s start address register
- spi_
smem_ timing_ cali - MSPI external RAM timing calibration register
- sram_
clk - SPI0 external RAM clock control register
- sram_
cmd - SPI0 external RAM mode control register
- sram_
drd_ cmd - SPI0 external RAM DDR read command control register
- sram_
dwr_ cmd - SPI0 external RAM DDR write command control register
- timing_
cali - SPI0 flash timing calibration register
- user
- SPI0 user register.
- user1
- SPI0 user1 register.
- user2
- SPI0 user2 register.
- xts_
date - Manual Encryption version register
- xts_
destination - Manual Encryption destination register
- xts_
destroy - Manual Encryption physical address register
- xts_
linesize - Manual Encryption Line-Size register
- xts_
physical_ address - Manual Encryption physical address register
- xts_
plain_ base - The base address of the memory that stores plaintext in Manual Encryption
- xts_
release - Manual Encryption physical address register
- xts_
state - Manual Encryption physical address register
- xts_
trigger - Manual Encryption physical address register
Structs§
- Register
Block - Register block
Type Aliases§
- AXI_
ERR_ ADDR - AXI_ERR_ADDR (r) register accessor: SPI0 AXI request error address.
- CACHE_
FCTRL - CACHE_FCTRL (rw) register accessor: SPI0 bit mode control register.
- CACHE_
SCTRL - CACHE_SCTRL (r) register accessor: SPI0 external RAM control register
- CLOCK
- CLOCK (rw) register accessor: SPI clock division control register.
- CLOCK_
GATE - CLOCK_GATE (rw) register accessor: SPI0 clock gate register
- CMD
- CMD (r) register accessor: SPI0 FSM status register
- CTRL
- CTRL (rw) register accessor: SPI0 control register.
- CTRL1
- CTRL1 (rw) register accessor: SPI0 control1 register.
- CTRL2
- CTRL2 (rw) register accessor: SPI0 control2 register.
- DATE
- DATE (rw) register accessor: SPI0 version control register
- DDR
- DDR (r) register accessor: SPI0 flash DDR mode control register
- DIN_
MODE - DIN_MODE (rw) register accessor: MSPI flash input timing delay mode control register
- DIN_NUM
- DIN_NUM (rw) register accessor: MSPI flash input timing delay number control register
- DOUT_
MODE - DOUT_MODE (rw) register accessor: MSPI flash output timing adjustment control register
- DPA_
CTRL - DPA_CTRL (rw) register accessor: SPI memory cryption DPA register
- ECC_
CTRL - ECC_CTRL (rw) register accessor: MSPI ECC control register
- ECC_
ERR_ ADDR - ECC_ERR_ADDR (r) register accessor: MSPI ECC error address register
- FSM
- FSM (rw) register accessor: SPI0 FSM status register
- INT_CLR
- INT_CLR (rw) register accessor: SPI0 interrupt clear register
- INT_ENA
- INT_ENA (rw) register accessor: SPI0 interrupt enable register
- INT_RAW
- INT_RAW (rw) register accessor: SPI0 interrupt raw register
- INT_ST
- INT_ST (r) register accessor: SPI0 interrupt status register
- MISC
- MISC (rw) register accessor: SPI0 misc register
- MMU_
ITEM_ CONTENT - MMU_ITEM_CONTENT (rw) register accessor: MSPI-MMU item content register
- MMU_
ITEM_ INDEX - MMU_ITEM_INDEX (rw) register accessor: MSPI-MMU item index register
- MMU_
POWER_ CTRL - MMU_POWER_CTRL (rw) register accessor: MSPI MMU power control register
- PMS_
REJECT - PMS_REJECT (rw) register accessor: SPI1 access reject register
- RD_
STATUS - RD_STATUS (rw) register accessor: SPI0 read control register.
- REGISTERRND_
ECO_ HIGH - REGISTERRND_ECO_HIGH (r) register accessor: MSPI ECO high register
- REGISTERRND_
ECO_ LOW - REGISTERRND_ECO_LOW (r) register accessor: MSPI ECO low register
- SPI_
FMEM_ PMS_ ADDR - SPI_FMEM_PMS_ADDR (rw) register accessor: SPI1 flash ACE section %s start address register
- SPI_
FMEM_ PMS_ ATTR - SPI_FMEM_PMS_ATTR (rw) register accessor: MSPI flash ACE section %s attribute register
- SPI_
FMEM_ PMS_ SIZE - SPI_FMEM_PMS_SIZE (rw) register accessor: SPI1 flash ACE section %s start address register
- SPI_
SMEM_ AC - SPI_SMEM_AC (r) register accessor: MSPI external RAM ECC and SPI CS timing control register
- SPI_
SMEM_ DDR - SPI_SMEM_DDR (r) register accessor: SPI0 external RAM DDR mode control register
- SPI_
SMEM_ DIN_ MODE - SPI_SMEM_DIN_MODE (r) register accessor: MSPI external RAM input timing delay mode control register
- SPI_
SMEM_ DIN_ NUM - SPI_SMEM_DIN_NUM (r) register accessor: MSPI external RAM input timing delay number control register
- SPI_
SMEM_ DOUT_ MODE - SPI_SMEM_DOUT_MODE (r) register accessor: MSPI external RAM output timing adjustment control register
- SPI_
SMEM_ ECC_ CTRL - SPI_SMEM_ECC_CTRL (r) register accessor: MSPI ECC control register
- SPI_
SMEM_ PMS_ ADDR - SPI_SMEM_PMS_ADDR (rw) register accessor: SPI1 external RAM ACE section %s start address register
- SPI_
SMEM_ PMS_ ATTR - SPI_SMEM_PMS_ATTR (rw) register accessor: SPI1 flash ACE section %s start address register
- SPI_
SMEM_ PMS_ SIZE - SPI_SMEM_PMS_SIZE (rw) register accessor: SPI1 external RAM ACE section %s start address register
- SPI_
SMEM_ TIMING_ CALI - SPI_SMEM_TIMING_CALI (r) register accessor: MSPI external RAM timing calibration register
- SRAM_
CLK - SRAM_CLK (r) register accessor: SPI0 external RAM clock control register
- SRAM_
CMD - SRAM_CMD (rw) register accessor: SPI0 external RAM mode control register
- SRAM_
DRD_ CMD - SRAM_DRD_CMD (r) register accessor: SPI0 external RAM DDR read command control register
- SRAM_
DWR_ CMD - SRAM_DWR_CMD (r) register accessor: SPI0 external RAM DDR write command control register
- TIMING_
CALI - TIMING_CALI (rw) register accessor: SPI0 flash timing calibration register
- USER
- USER (rw) register accessor: SPI0 user register.
- USER1
- USER1 (rw) register accessor: SPI0 user1 register.
- USER2
- USER2 (rw) register accessor: SPI0 user2 register.
- XTS_
DATE - XTS_DATE (rw) register accessor: Manual Encryption version register
- XTS_
DESTINATION - XTS_DESTINATION (rw) register accessor: Manual Encryption destination register
- XTS_
DESTROY - XTS_DESTROY (w) register accessor: Manual Encryption physical address register
- XTS_
LINESIZE - XTS_LINESIZE (rw) register accessor: Manual Encryption Line-Size register
- XTS_
PHYSICAL_ ADDRESS - XTS_PHYSICAL_ADDRESS (rw) register accessor: Manual Encryption physical address register
- XTS_
PLAIN_ BASE - XTS_PLAIN_BASE (rw) register accessor: The base address of the memory that stores plaintext in Manual Encryption
- XTS_
RELEASE - XTS_RELEASE (w) register accessor: Manual Encryption physical address register
- XTS_
STATE - XTS_STATE (r) register accessor: Manual Encryption physical address register
- XTS_
TRIGGER - XTS_TRIGGER (w) register accessor: Manual Encryption physical address register