Module conf

Timer 0 configuration

Structs

CONF_SPEC

Timer 0 configuration

Type Aliases

CLK_DIV_R

Field CLK_DIV reader - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.

CLK_DIV_W

Field CLK_DIV writer - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.

DUTY_RES_R

Field DUTY_RES reader - This register is used to control the range of the counter in timer %s.

DUTY_RES_W

Field DUTY_RES writer - This register is used to control the range of the counter in timer %s.

PARA_UP_W

Field PARA_UP writer - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.

PAUSE_R

Field PAUSE reader - This bit is used to suspend the counter in timer %s.

PAUSE_W

Field PAUSE writer - This bit is used to suspend the counter in timer %s.

R

Register CONF reader

RST_R

Field RST reader - This bit is used to reset timer %s. The counter will show 0 after reset.

RST_W

Field RST writer - This bit is used to reset timer %s. The counter will show 0 after reset.

TICK_SEL_R

Field TICK_SEL reader - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK

TICK_SEL_W

Field TICK_SEL writer - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK

W

Register CONF writer