1#[doc = "Register `CONF1` reader"]
2pub type R = crate::R<CONF1_SPEC>;
3#[doc = "Register `CONF1` writer"]
4pub type W = crate::W<CONF1_SPEC>;
5#[doc = "Field `RXFIFO_FULL_THRHD` reader - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
6pub type RXFIFO_FULL_THRHD_R = crate::FieldReader;
7#[doc = "Field `RXFIFO_FULL_THRHD` writer - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
8pub type RXFIFO_FULL_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `TXFIFO_EMPTY_THRHD` reader - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."]
10pub type TXFIFO_EMPTY_THRHD_R = crate::FieldReader;
11#[doc = "Field `TXFIFO_EMPTY_THRHD` writer - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."]
12pub type TXFIFO_EMPTY_THRHD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `CTS_INV` reader - Set this bit to inverse the level value of uart cts signal."]
14pub type CTS_INV_R = crate::BitReader;
15#[doc = "Field `CTS_INV` writer - Set this bit to inverse the level value of uart cts signal."]
16pub type CTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DSR_INV` reader - Set this bit to inverse the level value of uart dsr signal."]
18pub type DSR_INV_R = crate::BitReader;
19#[doc = "Field `DSR_INV` writer - Set this bit to inverse the level value of uart dsr signal."]
20pub type DSR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RTS_INV` reader - Set this bit to inverse the level value of uart rts signal."]
22pub type RTS_INV_R = crate::BitReader;
23#[doc = "Field `RTS_INV` writer - Set this bit to inverse the level value of uart rts signal."]
24pub type RTS_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DTR_INV` reader - Set this bit to inverse the level value of uart dtr signal."]
26pub type DTR_INV_R = crate::BitReader;
27#[doc = "Field `DTR_INV` writer - Set this bit to inverse the level value of uart dtr signal."]
28pub type DTR_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SW_DTR` reader - This register is used to configure the software dtr signal which is used in software flow control."]
30pub type SW_DTR_R = crate::BitReader;
31#[doc = "Field `SW_DTR` writer - This register is used to configure the software dtr signal which is used in software flow control."]
32pub type SW_DTR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
34pub type CLK_EN_R = crate::BitReader;
35#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
36pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
39 #[inline(always)]
40 pub fn rxfifo_full_thrhd(&self) -> RXFIFO_FULL_THRHD_R {
41 RXFIFO_FULL_THRHD_R::new((self.bits & 0xff) as u8)
42 }
43 #[doc = "Bits 8:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."]
44 #[inline(always)]
45 pub fn txfifo_empty_thrhd(&self) -> TXFIFO_EMPTY_THRHD_R {
46 TXFIFO_EMPTY_THRHD_R::new(((self.bits >> 8) & 0xff) as u8)
47 }
48 #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."]
49 #[inline(always)]
50 pub fn cts_inv(&self) -> CTS_INV_R {
51 CTS_INV_R::new(((self.bits >> 16) & 1) != 0)
52 }
53 #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."]
54 #[inline(always)]
55 pub fn dsr_inv(&self) -> DSR_INV_R {
56 DSR_INV_R::new(((self.bits >> 17) & 1) != 0)
57 }
58 #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."]
59 #[inline(always)]
60 pub fn rts_inv(&self) -> RTS_INV_R {
61 RTS_INV_R::new(((self.bits >> 18) & 1) != 0)
62 }
63 #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."]
64 #[inline(always)]
65 pub fn dtr_inv(&self) -> DTR_INV_R {
66 DTR_INV_R::new(((self.bits >> 19) & 1) != 0)
67 }
68 #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."]
69 #[inline(always)]
70 pub fn sw_dtr(&self) -> SW_DTR_R {
71 SW_DTR_R::new(((self.bits >> 20) & 1) != 0)
72 }
73 #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
74 #[inline(always)]
75 pub fn clk_en(&self) -> CLK_EN_R {
76 CLK_EN_R::new(((self.bits >> 21) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("CONF1")
83 .field("rxfifo_full_thrhd", &self.rxfifo_full_thrhd())
84 .field("txfifo_empty_thrhd", &self.txfifo_empty_thrhd())
85 .field("cts_inv", &self.cts_inv())
86 .field("dsr_inv", &self.dsr_inv())
87 .field("rts_inv", &self.rts_inv())
88 .field("dtr_inv", &self.dtr_inv())
89 .field("sw_dtr", &self.sw_dtr())
90 .field("clk_en", &self.clk_en())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bits 0:7 - It will produce rxfifo_full_int interrupt when receiver receives more data than this register value."]
96 #[inline(always)]
97 pub fn rxfifo_full_thrhd(&mut self) -> RXFIFO_FULL_THRHD_W<CONF1_SPEC> {
98 RXFIFO_FULL_THRHD_W::new(self, 0)
99 }
100 #[doc = "Bits 8:15 - It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value."]
101 #[inline(always)]
102 pub fn txfifo_empty_thrhd(&mut self) -> TXFIFO_EMPTY_THRHD_W<CONF1_SPEC> {
103 TXFIFO_EMPTY_THRHD_W::new(self, 8)
104 }
105 #[doc = "Bit 16 - Set this bit to inverse the level value of uart cts signal."]
106 #[inline(always)]
107 pub fn cts_inv(&mut self) -> CTS_INV_W<CONF1_SPEC> {
108 CTS_INV_W::new(self, 16)
109 }
110 #[doc = "Bit 17 - Set this bit to inverse the level value of uart dsr signal."]
111 #[inline(always)]
112 pub fn dsr_inv(&mut self) -> DSR_INV_W<CONF1_SPEC> {
113 DSR_INV_W::new(self, 17)
114 }
115 #[doc = "Bit 18 - Set this bit to inverse the level value of uart rts signal."]
116 #[inline(always)]
117 pub fn rts_inv(&mut self) -> RTS_INV_W<CONF1_SPEC> {
118 RTS_INV_W::new(self, 18)
119 }
120 #[doc = "Bit 19 - Set this bit to inverse the level value of uart dtr signal."]
121 #[inline(always)]
122 pub fn dtr_inv(&mut self) -> DTR_INV_W<CONF1_SPEC> {
123 DTR_INV_W::new(self, 19)
124 }
125 #[doc = "Bit 20 - This register is used to configure the software dtr signal which is used in software flow control."]
126 #[inline(always)]
127 pub fn sw_dtr(&mut self) -> SW_DTR_W<CONF1_SPEC> {
128 SW_DTR_W::new(self, 20)
129 }
130 #[doc = "Bit 21 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
131 #[inline(always)]
132 pub fn clk_en(&mut self) -> CLK_EN_W<CONF1_SPEC> {
133 CLK_EN_W::new(self, 21)
134 }
135}
136#[doc = "Configuration register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct CONF1_SPEC;
138impl crate::RegisterSpec for CONF1_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`conf1::R`](R) reader structure"]
142impl crate::Readable for CONF1_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`conf1::W`](W) writer structure"]
144impl crate::Writable for CONF1_SPEC {
145 type Safety = crate::Unsafe;
146 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets CONF1 to value 0x6060"]
150impl crate::Resettable for CONF1_SPEC {
151 const RESET_VALUE: u32 = 0x6060;
152}