esp32c6/slchost/
rdclr1.rs

1#[doc = "Register `RDCLR1` reader"]
2pub type R = crate::R<RDCLR1_SPEC>;
3#[doc = "Register `RDCLR1` writer"]
4pub type W = crate::W<RDCLR1_SPEC>;
5#[doc = "Field `SLCHOST_SLC1_BIT7_CLRADDR` reader - *******Description***********"]
6pub type SLCHOST_SLC1_BIT7_CLRADDR_R = crate::FieldReader<u16>;
7#[doc = "Field `SLCHOST_SLC1_BIT7_CLRADDR` writer - *******Description***********"]
8pub type SLCHOST_SLC1_BIT7_CLRADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `SLCHOST_SLC1_BIT6_CLRADDR` reader - *******Description***********"]
10pub type SLCHOST_SLC1_BIT6_CLRADDR_R = crate::FieldReader<u16>;
11#[doc = "Field `SLCHOST_SLC1_BIT6_CLRADDR` writer - *******Description***********"]
12pub type SLCHOST_SLC1_BIT6_CLRADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
13impl R {
14    #[doc = "Bits 0:8 - *******Description***********"]
15    #[inline(always)]
16    pub fn slchost_slc1_bit7_clraddr(&self) -> SLCHOST_SLC1_BIT7_CLRADDR_R {
17        SLCHOST_SLC1_BIT7_CLRADDR_R::new((self.bits & 0x01ff) as u16)
18    }
19    #[doc = "Bits 9:17 - *******Description***********"]
20    #[inline(always)]
21    pub fn slchost_slc1_bit6_clraddr(&self) -> SLCHOST_SLC1_BIT6_CLRADDR_R {
22        SLCHOST_SLC1_BIT6_CLRADDR_R::new(((self.bits >> 9) & 0x01ff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("RDCLR1")
29            .field(
30                "slchost_slc1_bit7_clraddr",
31                &self.slchost_slc1_bit7_clraddr(),
32            )
33            .field(
34                "slchost_slc1_bit6_clraddr",
35                &self.slchost_slc1_bit6_clraddr(),
36            )
37            .finish()
38    }
39}
40impl W {
41    #[doc = "Bits 0:8 - *******Description***********"]
42    #[inline(always)]
43    pub fn slchost_slc1_bit7_clraddr(&mut self) -> SLCHOST_SLC1_BIT7_CLRADDR_W<RDCLR1_SPEC> {
44        SLCHOST_SLC1_BIT7_CLRADDR_W::new(self, 0)
45    }
46    #[doc = "Bits 9:17 - *******Description***********"]
47    #[inline(always)]
48    pub fn slchost_slc1_bit6_clraddr(&mut self) -> SLCHOST_SLC1_BIT6_CLRADDR_W<RDCLR1_SPEC> {
49        SLCHOST_SLC1_BIT6_CLRADDR_W::new(self, 9)
50    }
51}
52#[doc = "*******Description***********\n\nYou can [`read`](crate::Reg::read) this register and get [`rdclr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rdclr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
53pub struct RDCLR1_SPEC;
54impl crate::RegisterSpec for RDCLR1_SPEC {
55    type Ux = u32;
56}
57#[doc = "`read()` method returns [`rdclr1::R`](R) reader structure"]
58impl crate::Readable for RDCLR1_SPEC {}
59#[doc = "`write(|w| ..)` method takes [`rdclr1::W`](W) writer structure"]
60impl crate::Writable for RDCLR1_SPEC {
61    type Safety = crate::Unsafe;
62    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
63    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
64}
65#[doc = "`reset()` method sets RDCLR1 to value 0x0003_c1e0"]
66impl crate::Resettable for RDCLR1_SPEC {
67    const RESET_VALUE: u32 = 0x0003_c1e0;
68}
esp32c6/slchost/rdclr1.rs

esp32c6/slchost/
rdclr1.rs
