esp32c6/plic_ux/
uxint_enable.rs

1#[doc = "Register `UXINT_ENABLE` reader"]
2pub type R = crate::R<UXINT_ENABLE_SPEC>;
3#[doc = "Register `UXINT_ENABLE` writer"]
4pub type W = crate::W<UXINT_ENABLE_SPEC>;
5#[doc = "Field `CPU_UXINT_ENABLE` reader - "]
6pub type CPU_UXINT_ENABLE_R = crate::FieldReader<u32>;
7#[doc = "Field `CPU_UXINT_ENABLE` writer - "]
8pub type CPU_UXINT_ENABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31"]
11    #[inline(always)]
12    pub fn cpu_uxint_enable(&self) -> CPU_UXINT_ENABLE_R {
13        CPU_UXINT_ENABLE_R::new(self.bits)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("UXINT_ENABLE")
20            .field("cpu_uxint_enable", &self.cpu_uxint_enable())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:31"]
26    #[inline(always)]
27    pub fn cpu_uxint_enable(&mut self) -> CPU_UXINT_ENABLE_W<UXINT_ENABLE_SPEC> {
28        CPU_UXINT_ENABLE_W::new(self, 0)
29    }
30}
31#[doc = "PLIC UX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_enable::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_enable::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct UXINT_ENABLE_SPEC;
33impl crate::RegisterSpec for UXINT_ENABLE_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`uxint_enable::R`](R) reader structure"]
37impl crate::Readable for UXINT_ENABLE_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`uxint_enable::W`](W) writer structure"]
39impl crate::Writable for UXINT_ENABLE_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets UXINT_ENABLE to value 0"]
45impl crate::Resettable for UXINT_ENABLE_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
esp32c6/plic_ux/uxint_enable.rs

esp32c6/plic_ux/
uxint_enable.rs
