esp32c6/pcnt/
int_raw.rs

1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Field `CNT_THR_EVENT_U(0-3)` reader - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U%s_INT interrupt."]
4pub type CNT_THR_EVENT_U_R = crate::BitReader;
5impl R {
6    #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
7    #[doc = ""]
8    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CNT_THR_EVENT_U0` field.</div>"]
9    #[inline(always)]
10    pub fn cnt_thr_event_u(&self, n: u8) -> CNT_THR_EVENT_U_R {
11        #[allow(clippy::no_effect)]
12        [(); 4][n as usize];
13        CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0)
14    }
15    #[doc = "Iterator for array of:"]
16    #[doc = "The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U(0-3)_INT interrupt."]
17    #[inline(always)]
18    pub fn cnt_thr_event_u_iter(&self) -> impl Iterator<Item = CNT_THR_EVENT_U_R> + '_ {
19        (0..4).map(move |n| CNT_THR_EVENT_U_R::new(((self.bits >> n) & 1) != 0))
20    }
21    #[doc = "Bit 0 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt."]
22    #[inline(always)]
23    pub fn cnt_thr_event_u0(&self) -> CNT_THR_EVENT_U_R {
24        CNT_THR_EVENT_U_R::new((self.bits & 1) != 0)
25    }
26    #[doc = "Bit 1 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt."]
27    #[inline(always)]
28    pub fn cnt_thr_event_u1(&self) -> CNT_THR_EVENT_U_R {
29        CNT_THR_EVENT_U_R::new(((self.bits >> 1) & 1) != 0)
30    }
31    #[doc = "Bit 2 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt."]
32    #[inline(always)]
33    pub fn cnt_thr_event_u2(&self) -> CNT_THR_EVENT_U_R {
34        CNT_THR_EVENT_U_R::new(((self.bits >> 2) & 1) != 0)
35    }
36    #[doc = "Bit 3 - The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt."]
37    #[inline(always)]
38    pub fn cnt_thr_event_u3(&self) -> CNT_THR_EVENT_U_R {
39        CNT_THR_EVENT_U_R::new(((self.bits >> 3) & 1) != 0)
40    }
41}
42#[cfg(feature = "impl-register-debug")]
43impl core::fmt::Debug for R {
44    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45        f.debug_struct("INT_RAW")
46            .field("cnt_thr_event_u0", &self.cnt_thr_event_u0())
47            .field("cnt_thr_event_u1", &self.cnt_thr_event_u1())
48            .field("cnt_thr_event_u2", &self.cnt_thr_event_u2())
49            .field("cnt_thr_event_u3", &self.cnt_thr_event_u3())
50            .finish()
51    }
52}
53#[doc = "Interrupt raw status register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct INT_RAW_SPEC;
55impl crate::RegisterSpec for INT_RAW_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
59impl crate::Readable for INT_RAW_SPEC {}
60#[doc = "`reset()` method sets INT_RAW to value 0"]
61impl crate::Resettable for INT_RAW_SPEC {
62    const RESET_VALUE: u32 = 0;
63}
esp32c6/pcnt/int_raw.rs

esp32c6/pcnt/
int_raw.rs
