esp32c6/lp_i2c0/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RXFIFO_WM` reader - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
6pub type RXFIFO_WM_R = crate::BitReader;
7#[doc = "Field `RXFIFO_WM` writer - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
8pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_WM` reader - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."]
10pub type TXFIFO_WM_R = crate::BitReader;
11#[doc = "Field `TXFIFO_WM` writer - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."]
12pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RXFIFO_OVF` reader - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."]
14pub type RXFIFO_OVF_R = crate::BitReader;
15#[doc = "Field `RXFIFO_OVF` writer - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."]
16pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `END_DETECT` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
18pub type END_DETECT_R = crate::BitReader;
19#[doc = "Field `END_DETECT` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
20pub type END_DETECT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `BYTE_TRANS_DONE` reader - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
22pub type BYTE_TRANS_DONE_R = crate::BitReader;
23#[doc = "Field `BYTE_TRANS_DONE` writer - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
24pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `ARBITRATION_LOST` reader - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."]
26pub type ARBITRATION_LOST_R = crate::BitReader;
27#[doc = "Field `ARBITRATION_LOST` writer - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."]
28pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MST_TXFIFO_UDF` reader - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."]
30pub type MST_TXFIFO_UDF_R = crate::BitReader;
31#[doc = "Field `MST_TXFIFO_UDF` writer - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."]
32pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `TRANS_COMPLETE` reader - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."]
34pub type TRANS_COMPLETE_R = crate::BitReader;
35#[doc = "Field `TRANS_COMPLETE` writer - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."]
36pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TIME_OUT` reader - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."]
38pub type TIME_OUT_R = crate::BitReader;
39#[doc = "Field `TIME_OUT` writer - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."]
40pub type TIME_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `TRANS_START` reader - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."]
42pub type TRANS_START_R = crate::BitReader;
43#[doc = "Field `TRANS_START` writer - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."]
44pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `NACK` reader - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
46pub type NACK_R = crate::BitReader;
47#[doc = "Field `NACK` writer - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
48pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `TXFIFO_OVF` reader - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."]
50pub type TXFIFO_OVF_R = crate::BitReader;
51#[doc = "Field `TXFIFO_OVF` writer - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."]
52pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `RXFIFO_UDF` reader - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."]
54pub type RXFIFO_UDF_R = crate::BitReader;
55#[doc = "Field `RXFIFO_UDF` writer - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."]
56pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `SCL_ST_TO` reader - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."]
58pub type SCL_ST_TO_R = crate::BitReader;
59#[doc = "Field `SCL_ST_TO` writer - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."]
60pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `SCL_MAIN_ST_TO` reader - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
62pub type SCL_MAIN_ST_TO_R = crate::BitReader;
63#[doc = "Field `SCL_MAIN_ST_TO` writer - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
64pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `DET_START` reader - The interrupt enable bit for I2C_DET_START_INT interrupt."]
66pub type DET_START_R = crate::BitReader;
67#[doc = "Field `DET_START` writer - The interrupt enable bit for I2C_DET_START_INT interrupt."]
68pub type DET_START_W<'a, REG> = crate::BitWriter<'a, REG>;
69impl R {
70    #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
71    #[inline(always)]
72    pub fn rxfifo_wm(&self) -> RXFIFO_WM_R {
73        RXFIFO_WM_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."]
76    #[inline(always)]
77    pub fn txfifo_wm(&self) -> TXFIFO_WM_R {
78        TXFIFO_WM_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."]
81    #[inline(always)]
82    pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
83        RXFIFO_OVF_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
86    #[inline(always)]
87    pub fn end_detect(&self) -> END_DETECT_R {
88        END_DETECT_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
91    #[inline(always)]
92    pub fn byte_trans_done(&self) -> BYTE_TRANS_DONE_R {
93        BYTE_TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."]
96    #[inline(always)]
97    pub fn arbitration_lost(&self) -> ARBITRATION_LOST_R {
98        ARBITRATION_LOST_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."]
101    #[inline(always)]
102    pub fn mst_txfifo_udf(&self) -> MST_TXFIFO_UDF_R {
103        MST_TXFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."]
106    #[inline(always)]
107    pub fn trans_complete(&self) -> TRANS_COMPLETE_R {
108        TRANS_COMPLETE_R::new(((self.bits >> 7) & 1) != 0)
109    }
110    #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."]
111    #[inline(always)]
112    pub fn time_out(&self) -> TIME_OUT_R {
113        TIME_OUT_R::new(((self.bits >> 8) & 1) != 0)
114    }
115    #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."]
116    #[inline(always)]
117    pub fn trans_start(&self) -> TRANS_START_R {
118        TRANS_START_R::new(((self.bits >> 9) & 1) != 0)
119    }
120    #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
121    #[inline(always)]
122    pub fn nack(&self) -> NACK_R {
123        NACK_R::new(((self.bits >> 10) & 1) != 0)
124    }
125    #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."]
126    #[inline(always)]
127    pub fn txfifo_ovf(&self) -> TXFIFO_OVF_R {
128        TXFIFO_OVF_R::new(((self.bits >> 11) & 1) != 0)
129    }
130    #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."]
131    #[inline(always)]
132    pub fn rxfifo_udf(&self) -> RXFIFO_UDF_R {
133        RXFIFO_UDF_R::new(((self.bits >> 12) & 1) != 0)
134    }
135    #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."]
136    #[inline(always)]
137    pub fn scl_st_to(&self) -> SCL_ST_TO_R {
138        SCL_ST_TO_R::new(((self.bits >> 13) & 1) != 0)
139    }
140    #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
141    #[inline(always)]
142    pub fn scl_main_st_to(&self) -> SCL_MAIN_ST_TO_R {
143        SCL_MAIN_ST_TO_R::new(((self.bits >> 14) & 1) != 0)
144    }
145    #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."]
146    #[inline(always)]
147    pub fn det_start(&self) -> DET_START_R {
148        DET_START_R::new(((self.bits >> 15) & 1) != 0)
149    }
150}
151#[cfg(feature = "impl-register-debug")]
152impl core::fmt::Debug for R {
153    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
154        f.debug_struct("INT_ENA")
155            .field("rxfifo_wm", &self.rxfifo_wm())
156            .field("txfifo_wm", &self.txfifo_wm())
157            .field("rxfifo_ovf", &self.rxfifo_ovf())
158            .field("end_detect", &self.end_detect())
159            .field("byte_trans_done", &self.byte_trans_done())
160            .field("arbitration_lost", &self.arbitration_lost())
161            .field("mst_txfifo_udf", &self.mst_txfifo_udf())
162            .field("trans_complete", &self.trans_complete())
163            .field("time_out", &self.time_out())
164            .field("trans_start", &self.trans_start())
165            .field("nack", &self.nack())
166            .field("txfifo_ovf", &self.txfifo_ovf())
167            .field("rxfifo_udf", &self.rxfifo_udf())
168            .field("scl_st_to", &self.scl_st_to())
169            .field("scl_main_st_to", &self.scl_main_st_to())
170            .field("det_start", &self.det_start())
171            .finish()
172    }
173}
174impl W {
175    #[doc = "Bit 0 - The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt."]
176    #[inline(always)]
177    pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_ENA_SPEC> {
178        RXFIFO_WM_W::new(self, 0)
179    }
180    #[doc = "Bit 1 - The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt."]
181    #[inline(always)]
182    pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_ENA_SPEC> {
183        TXFIFO_WM_W::new(self, 1)
184    }
185    #[doc = "Bit 2 - The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt."]
186    #[inline(always)]
187    pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
188        RXFIFO_OVF_W::new(self, 2)
189    }
190    #[doc = "Bit 3 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
191    #[inline(always)]
192    pub fn end_detect(&mut self) -> END_DETECT_W<INT_ENA_SPEC> {
193        END_DETECT_W::new(self, 3)
194    }
195    #[doc = "Bit 4 - The interrupt enable bit for the I2C_END_DETECT_INT interrupt."]
196    #[inline(always)]
197    pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_ENA_SPEC> {
198        BYTE_TRANS_DONE_W::new(self, 4)
199    }
200    #[doc = "Bit 5 - The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt."]
201    #[inline(always)]
202    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_ENA_SPEC> {
203        ARBITRATION_LOST_W::new(self, 5)
204    }
205    #[doc = "Bit 6 - The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt."]
206    #[inline(always)]
207    pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_ENA_SPEC> {
208        MST_TXFIFO_UDF_W::new(self, 6)
209    }
210    #[doc = "Bit 7 - The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt."]
211    #[inline(always)]
212    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_ENA_SPEC> {
213        TRANS_COMPLETE_W::new(self, 7)
214    }
215    #[doc = "Bit 8 - The interrupt enable bit for the I2C_TIME_OUT_INT interrupt."]
216    #[inline(always)]
217    pub fn time_out(&mut self) -> TIME_OUT_W<INT_ENA_SPEC> {
218        TIME_OUT_W::new(self, 8)
219    }
220    #[doc = "Bit 9 - The interrupt enable bit for the I2C_TRANS_START_INT interrupt."]
221    #[inline(always)]
222    pub fn trans_start(&mut self) -> TRANS_START_W<INT_ENA_SPEC> {
223        TRANS_START_W::new(self, 9)
224    }
225    #[doc = "Bit 10 - The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt."]
226    #[inline(always)]
227    pub fn nack(&mut self) -> NACK_W<INT_ENA_SPEC> {
228        NACK_W::new(self, 10)
229    }
230    #[doc = "Bit 11 - The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt."]
231    #[inline(always)]
232    pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_ENA_SPEC> {
233        TXFIFO_OVF_W::new(self, 11)
234    }
235    #[doc = "Bit 12 - The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt."]
236    #[inline(always)]
237    pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_ENA_SPEC> {
238        RXFIFO_UDF_W::new(self, 12)
239    }
240    #[doc = "Bit 13 - The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt."]
241    #[inline(always)]
242    pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_ENA_SPEC> {
243        SCL_ST_TO_W::new(self, 13)
244    }
245    #[doc = "Bit 14 - The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt."]
246    #[inline(always)]
247    pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_ENA_SPEC> {
248        SCL_MAIN_ST_TO_W::new(self, 14)
249    }
250    #[doc = "Bit 15 - The interrupt enable bit for I2C_DET_START_INT interrupt."]
251    #[inline(always)]
252    pub fn det_start(&mut self) -> DET_START_W<INT_ENA_SPEC> {
253        DET_START_W::new(self, 15)
254    }
255}
256#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct INT_ENA_SPEC;
258impl crate::RegisterSpec for INT_ENA_SPEC {
259    type Ux = u32;
260}
261#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
262impl crate::Readable for INT_ENA_SPEC {}
263#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
264impl crate::Writable for INT_ENA_SPEC {
265    type Safety = crate::Unsafe;
266    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268}
269#[doc = "`reset()` method sets INT_ENA to value 0"]
270impl crate::Resettable for INT_ENA_SPEC {
271    const RESET_VALUE: u32 = 0;
272}