esp32c6/lp_i2c0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_WM` writer - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
4pub type RXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_WM` writer - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
6pub type TXFIFO_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
8pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `END_DETECT` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
10pub type END_DETECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `BYTE_TRANS_DONE` writer - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
12pub type BYTE_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `ARBITRATION_LOST` writer - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
14pub type ARBITRATION_LOST_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `MST_TXFIFO_UDF` writer - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
16pub type MST_TXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TRANS_COMPLETE` writer - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
18pub type TRANS_COMPLETE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `TIME_OUT` writer - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
20pub type TIME_OUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `TRANS_START` writer - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `NACK` writer - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
24pub type NACK_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `TXFIFO_OVF` writer - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
26pub type TXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `RXFIFO_UDF` writer - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
28pub type RXFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `SCL_ST_TO` writer - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
30pub type SCL_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SCL_MAIN_ST_TO` writer - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
32pub type SCL_MAIN_ST_TO_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `DET_START` writer - Set this bit to clear I2C_DET_START_INT interrupt."]
34pub type DET_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[cfg(feature = "impl-register-debug")]
36impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
37    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
38        write!(f, "(not readable)")
39    }
40}
41impl W {
42    #[doc = "Bit 0 - Set this bit to clear I2C_RXFIFO_WM_INT interrupt."]
43    #[inline(always)]
44    pub fn rxfifo_wm(&mut self) -> RXFIFO_WM_W<INT_CLR_SPEC> {
45        RXFIFO_WM_W::new(self, 0)
46    }
47    #[doc = "Bit 1 - Set this bit to clear I2C_TXFIFO_WM_INT interrupt."]
48    #[inline(always)]
49    pub fn txfifo_wm(&mut self) -> TXFIFO_WM_W<INT_CLR_SPEC> {
50        TXFIFO_WM_W::new(self, 1)
51    }
52    #[doc = "Bit 2 - Set this bit to clear I2C_RXFIFO_OVF_INT interrupt."]
53    #[inline(always)]
54    pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
55        RXFIFO_OVF_W::new(self, 2)
56    }
57    #[doc = "Bit 3 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
58    #[inline(always)]
59    pub fn end_detect(&mut self) -> END_DETECT_W<INT_CLR_SPEC> {
60        END_DETECT_W::new(self, 3)
61    }
62    #[doc = "Bit 4 - Set this bit to clear the I2C_END_DETECT_INT interrupt."]
63    #[inline(always)]
64    pub fn byte_trans_done(&mut self) -> BYTE_TRANS_DONE_W<INT_CLR_SPEC> {
65        BYTE_TRANS_DONE_W::new(self, 4)
66    }
67    #[doc = "Bit 5 - Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt."]
68    #[inline(always)]
69    pub fn arbitration_lost(&mut self) -> ARBITRATION_LOST_W<INT_CLR_SPEC> {
70        ARBITRATION_LOST_W::new(self, 5)
71    }
72    #[doc = "Bit 6 - Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt."]
73    #[inline(always)]
74    pub fn mst_txfifo_udf(&mut self) -> MST_TXFIFO_UDF_W<INT_CLR_SPEC> {
75        MST_TXFIFO_UDF_W::new(self, 6)
76    }
77    #[doc = "Bit 7 - Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt."]
78    #[inline(always)]
79    pub fn trans_complete(&mut self) -> TRANS_COMPLETE_W<INT_CLR_SPEC> {
80        TRANS_COMPLETE_W::new(self, 7)
81    }
82    #[doc = "Bit 8 - Set this bit to clear the I2C_TIME_OUT_INT interrupt."]
83    #[inline(always)]
84    pub fn time_out(&mut self) -> TIME_OUT_W<INT_CLR_SPEC> {
85        TIME_OUT_W::new(self, 8)
86    }
87    #[doc = "Bit 9 - Set this bit to clear the I2C_TRANS_START_INT interrupt."]
88    #[inline(always)]
89    pub fn trans_start(&mut self) -> TRANS_START_W<INT_CLR_SPEC> {
90        TRANS_START_W::new(self, 9)
91    }
92    #[doc = "Bit 10 - Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt."]
93    #[inline(always)]
94    pub fn nack(&mut self) -> NACK_W<INT_CLR_SPEC> {
95        NACK_W::new(self, 10)
96    }
97    #[doc = "Bit 11 - Set this bit to clear I2C_TXFIFO_OVF_INT interrupt."]
98    #[inline(always)]
99    pub fn txfifo_ovf(&mut self) -> TXFIFO_OVF_W<INT_CLR_SPEC> {
100        TXFIFO_OVF_W::new(self, 11)
101    }
102    #[doc = "Bit 12 - Set this bit to clear I2C_RXFIFO_UDF_INT interrupt."]
103    #[inline(always)]
104    pub fn rxfifo_udf(&mut self) -> RXFIFO_UDF_W<INT_CLR_SPEC> {
105        RXFIFO_UDF_W::new(self, 12)
106    }
107    #[doc = "Bit 13 - Set this bit to clear I2C_SCL_ST_TO_INT interrupt."]
108    #[inline(always)]
109    pub fn scl_st_to(&mut self) -> SCL_ST_TO_W<INT_CLR_SPEC> {
110        SCL_ST_TO_W::new(self, 13)
111    }
112    #[doc = "Bit 14 - Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt."]
113    #[inline(always)]
114    pub fn scl_main_st_to(&mut self) -> SCL_MAIN_ST_TO_W<INT_CLR_SPEC> {
115        SCL_MAIN_ST_TO_W::new(self, 14)
116    }
117    #[doc = "Bit 15 - Set this bit to clear I2C_DET_START_INT interrupt."]
118    #[inline(always)]
119    pub fn det_start(&mut self) -> DET_START_W<INT_CLR_SPEC> {
120        DET_START_W::new(self, 15)
121    }
122}
123#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
124pub struct INT_CLR_SPEC;
125impl crate::RegisterSpec for INT_CLR_SPEC {
126    type Ux = u32;
127}
128#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
129impl crate::Writable for INT_CLR_SPEC {
130    type Safety = crate::Unsafe;
131    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0xffff;
133}
134#[doc = "`reset()` method sets INT_CLR to value 0"]
135impl crate::Resettable for INT_CLR_SPEC {
136    const RESET_VALUE: u32 = 0;
137}
esp32c6/lp_i2c0/int_clr.rs

esp32c6/lp_i2c0/
int_clr.rs
