esp32c6/extmem/
l2_cache_sync_preload_int_st.rs

1#[doc = "Register `L2_CACHE_SYNC_PRELOAD_INT_ST` reader"]
2pub type R = crate::R<L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC>;
3#[doc = "Field `L2_CACHE_PLD_DONE_INT_ST` reader - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done."]
4pub type L2_CACHE_PLD_DONE_INT_ST_R = crate::BitReader;
5#[doc = "Field `L2_CACHE_PLD_ERR_INT_ST` reader - The bit indicates the status of the interrupt of L2-Cache preload-operation error."]
6pub type L2_CACHE_PLD_ERR_INT_ST_R = crate::BitReader;
7impl R {
8    #[doc = "Bit 5 - The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done."]
9    #[inline(always)]
10    pub fn l2_cache_pld_done_int_st(&self) -> L2_CACHE_PLD_DONE_INT_ST_R {
11        L2_CACHE_PLD_DONE_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
12    }
13    #[doc = "Bit 12 - The bit indicates the status of the interrupt of L2-Cache preload-operation error."]
14    #[inline(always)]
15    pub fn l2_cache_pld_err_int_st(&self) -> L2_CACHE_PLD_ERR_INT_ST_R {
16        L2_CACHE_PLD_ERR_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
17    }
18}
19#[cfg(feature = "impl-register-debug")]
20impl core::fmt::Debug for R {
21    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
22        f.debug_struct("L2_CACHE_SYNC_PRELOAD_INT_ST")
23            .field("l2_cache_pld_done_int_st", &self.l2_cache_pld_done_int_st())
24            .field("l2_cache_pld_err_int_st", &self.l2_cache_pld_err_int_st())
25            .finish()
26    }
27}
28#[doc = "L1-Cache Access Fail Interrupt status register\n\nYou can [`read`](crate::Reg::read) this register and get [`l2_cache_sync_preload_int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
29pub struct L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC;
30impl crate::RegisterSpec for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {
31    type Ux = u32;
32}
33#[doc = "`read()` method returns [`l2_cache_sync_preload_int_st::R`](R) reader structure"]
34impl crate::Readable for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {}
35#[doc = "`reset()` method sets L2_CACHE_SYNC_PRELOAD_INT_ST to value 0"]
36impl crate::Resettable for L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC {
37    const RESET_VALUE: u32 = 0;
38}
esp32c6/extmem/l2_cache_sync_preload_int_st.rs

esp32c6/extmem/
l2_cache_sync_preload_int_st.rs
