esp32c6/extmem/
l1_cache_preload_rst_ctrl.rs

1#[doc = "Register `L1_CACHE_PRELOAD_RST_CTRL` reader"]
2pub type R = crate::R<L1_CACHE_PRELOAD_RST_CTRL_SPEC>;
3#[doc = "Register `L1_CACHE_PRELOAD_RST_CTRL` writer"]
4pub type W = crate::W<L1_CACHE_PRELOAD_RST_CTRL_SPEC>;
5#[doc = "Field `L1_ICACHE0_PLD_RST` reader - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
6pub type L1_ICACHE0_PLD_RST_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE1_PLD_RST` reader - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
8pub type L1_ICACHE1_PLD_RST_R = crate::BitReader;
9#[doc = "Field `L1_ICACHE2_PLD_RST` reader - Reserved"]
10pub type L1_ICACHE2_PLD_RST_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE3_PLD_RST` reader - Reserved"]
12pub type L1_ICACHE3_PLD_RST_R = crate::BitReader;
13#[doc = "Field `L1_CACHE_PLD_RST` reader - set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
14pub type L1_CACHE_PLD_RST_R = crate::BitReader;
15#[doc = "Field `L1_CACHE_PLD_RST` writer - set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
16pub type L1_CACHE_PLD_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bit 0 - set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
19    #[inline(always)]
20    pub fn l1_icache0_pld_rst(&self) -> L1_ICACHE0_PLD_RST_R {
21        L1_ICACHE0_PLD_RST_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1 - set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
24    #[inline(always)]
25    pub fn l1_icache1_pld_rst(&self) -> L1_ICACHE1_PLD_RST_R {
26        L1_ICACHE1_PLD_RST_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bit 2 - Reserved"]
29    #[inline(always)]
30    pub fn l1_icache2_pld_rst(&self) -> L1_ICACHE2_PLD_RST_R {
31        L1_ICACHE2_PLD_RST_R::new(((self.bits >> 2) & 1) != 0)
32    }
33    #[doc = "Bit 3 - Reserved"]
34    #[inline(always)]
35    pub fn l1_icache3_pld_rst(&self) -> L1_ICACHE3_PLD_RST_R {
36        L1_ICACHE3_PLD_RST_R::new(((self.bits >> 3) & 1) != 0)
37    }
38    #[doc = "Bit 4 - set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
39    #[inline(always)]
40    pub fn l1_cache_pld_rst(&self) -> L1_CACHE_PLD_RST_R {
41        L1_CACHE_PLD_RST_R::new(((self.bits >> 4) & 1) != 0)
42    }
43}
44#[cfg(feature = "impl-register-debug")]
45impl core::fmt::Debug for R {
46    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
47        f.debug_struct("L1_CACHE_PRELOAD_RST_CTRL")
48            .field("l1_icache0_pld_rst", &self.l1_icache0_pld_rst())
49            .field("l1_icache1_pld_rst", &self.l1_icache1_pld_rst())
50            .field("l1_icache2_pld_rst", &self.l1_icache2_pld_rst())
51            .field("l1_icache3_pld_rst", &self.l1_icache3_pld_rst())
52            .field("l1_cache_pld_rst", &self.l1_cache_pld_rst())
53            .finish()
54    }
55}
56impl W {
57    #[doc = "Bit 4 - set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs."]
58    #[inline(always)]
59    pub fn l1_cache_pld_rst(&mut self) -> L1_CACHE_PLD_RST_W<L1_CACHE_PRELOAD_RST_CTRL_SPEC> {
60        L1_CACHE_PLD_RST_W::new(self, 4)
61    }
62}
63#[doc = "Cache Preload Reset control register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_preload_rst_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_cache_preload_rst_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
64pub struct L1_CACHE_PRELOAD_RST_CTRL_SPEC;
65impl crate::RegisterSpec for L1_CACHE_PRELOAD_RST_CTRL_SPEC {
66    type Ux = u32;
67}
68#[doc = "`read()` method returns [`l1_cache_preload_rst_ctrl::R`](R) reader structure"]
69impl crate::Readable for L1_CACHE_PRELOAD_RST_CTRL_SPEC {}
70#[doc = "`write(|w| ..)` method takes [`l1_cache_preload_rst_ctrl::W`](W) writer structure"]
71impl crate::Writable for L1_CACHE_PRELOAD_RST_CTRL_SPEC {
72    type Safety = crate::Unsafe;
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75}
76#[doc = "`reset()` method sets L1_CACHE_PRELOAD_RST_CTRL to value 0"]
77impl crate::Resettable for L1_CACHE_PRELOAD_RST_CTRL_SPEC {
78    const RESET_VALUE: u32 = 0;
79}
esp32c6/extmem/l1_cache_preload_rst_ctrl.rs

esp32c6/extmem/
l1_cache_preload_rst_ctrl.rs
