esp32c6/extmem/
l1_cache_acs_fail_int_raw.rs

1#[doc = "Register `L1_CACHE_ACS_FAIL_INT_RAW` reader"]
2pub type R = crate::R<L1_CACHE_ACS_FAIL_INT_RAW_SPEC>;
3#[doc = "Register `L1_CACHE_ACS_FAIL_INT_RAW` writer"]
4pub type W = crate::W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC>;
5#[doc = "Field `L1_ICACHE0_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
6pub type L1_ICACHE0_FAIL_INT_RAW_R = crate::BitReader;
7#[doc = "Field `L1_ICACHE0_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
8pub type L1_ICACHE0_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `L1_ICACHE1_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache1."]
10pub type L1_ICACHE1_FAIL_INT_RAW_R = crate::BitReader;
11#[doc = "Field `L1_ICACHE1_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache1."]
12pub type L1_ICACHE1_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `L1_ICACHE2_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache2."]
14pub type L1_ICACHE2_FAIL_INT_RAW_R = crate::BitReader;
15#[doc = "Field `L1_ICACHE2_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache2."]
16pub type L1_ICACHE2_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `L1_ICACHE3_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-ICache3."]
18pub type L1_ICACHE3_FAIL_INT_RAW_R = crate::BitReader;
19#[doc = "Field `L1_ICACHE3_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-ICache3."]
20pub type L1_ICACHE3_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `L1_CACHE_FAIL_INT_RAW` reader - The raw bit of the interrupt of access fail that occurs in L1-DCache."]
22pub type L1_CACHE_FAIL_INT_RAW_R = crate::BitReader;
23#[doc = "Field `L1_CACHE_FAIL_INT_RAW` writer - The raw bit of the interrupt of access fail that occurs in L1-DCache."]
24pub type L1_CACHE_FAIL_INT_RAW_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
27    #[inline(always)]
28    pub fn l1_icache0_fail_int_raw(&self) -> L1_ICACHE0_FAIL_INT_RAW_R {
29        L1_ICACHE0_FAIL_INT_RAW_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - The raw bit of the interrupt of access fail that occurs in L1-ICache1."]
32    #[inline(always)]
33    pub fn l1_icache1_fail_int_raw(&self) -> L1_ICACHE1_FAIL_INT_RAW_R {
34        L1_ICACHE1_FAIL_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - The raw bit of the interrupt of access fail that occurs in L1-ICache2."]
37    #[inline(always)]
38    pub fn l1_icache2_fail_int_raw(&self) -> L1_ICACHE2_FAIL_INT_RAW_R {
39        L1_ICACHE2_FAIL_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3 - The raw bit of the interrupt of access fail that occurs in L1-ICache3."]
42    #[inline(always)]
43    pub fn l1_icache3_fail_int_raw(&self) -> L1_ICACHE3_FAIL_INT_RAW_R {
44        L1_ICACHE3_FAIL_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4 - The raw bit of the interrupt of access fail that occurs in L1-DCache."]
47    #[inline(always)]
48    pub fn l1_cache_fail_int_raw(&self) -> L1_CACHE_FAIL_INT_RAW_R {
49        L1_CACHE_FAIL_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("L1_CACHE_ACS_FAIL_INT_RAW")
56            .field("l1_icache0_fail_int_raw", &self.l1_icache0_fail_int_raw())
57            .field("l1_icache1_fail_int_raw", &self.l1_icache1_fail_int_raw())
58            .field("l1_icache2_fail_int_raw", &self.l1_icache2_fail_int_raw())
59            .field("l1_icache3_fail_int_raw", &self.l1_icache3_fail_int_raw())
60            .field("l1_cache_fail_int_raw", &self.l1_cache_fail_int_raw())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0 - The raw bit of the interrupt of access fail that occurs in L1-ICache0."]
66    #[inline(always)]
67    pub fn l1_icache0_fail_int_raw(
68        &mut self,
69    ) -> L1_ICACHE0_FAIL_INT_RAW_W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
70        L1_ICACHE0_FAIL_INT_RAW_W::new(self, 0)
71    }
72    #[doc = "Bit 1 - The raw bit of the interrupt of access fail that occurs in L1-ICache1."]
73    #[inline(always)]
74    pub fn l1_icache1_fail_int_raw(
75        &mut self,
76    ) -> L1_ICACHE1_FAIL_INT_RAW_W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
77        L1_ICACHE1_FAIL_INT_RAW_W::new(self, 1)
78    }
79    #[doc = "Bit 2 - The raw bit of the interrupt of access fail that occurs in L1-ICache2."]
80    #[inline(always)]
81    pub fn l1_icache2_fail_int_raw(
82        &mut self,
83    ) -> L1_ICACHE2_FAIL_INT_RAW_W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
84        L1_ICACHE2_FAIL_INT_RAW_W::new(self, 2)
85    }
86    #[doc = "Bit 3 - The raw bit of the interrupt of access fail that occurs in L1-ICache3."]
87    #[inline(always)]
88    pub fn l1_icache3_fail_int_raw(
89        &mut self,
90    ) -> L1_ICACHE3_FAIL_INT_RAW_W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
91        L1_ICACHE3_FAIL_INT_RAW_W::new(self, 3)
92    }
93    #[doc = "Bit 4 - The raw bit of the interrupt of access fail that occurs in L1-DCache."]
94    #[inline(always)]
95    pub fn l1_cache_fail_int_raw(
96        &mut self,
97    ) -> L1_CACHE_FAIL_INT_RAW_W<L1_CACHE_ACS_FAIL_INT_RAW_SPEC> {
98        L1_CACHE_FAIL_INT_RAW_W::new(self, 4)
99    }
100}
101#[doc = "Cache Access Fail Interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`l1_cache_acs_fail_int_raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`l1_cache_acs_fail_int_raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
102pub struct L1_CACHE_ACS_FAIL_INT_RAW_SPEC;
103impl crate::RegisterSpec for L1_CACHE_ACS_FAIL_INT_RAW_SPEC {
104    type Ux = u32;
105}
106#[doc = "`read()` method returns [`l1_cache_acs_fail_int_raw::R`](R) reader structure"]
107impl crate::Readable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC {}
108#[doc = "`write(|w| ..)` method takes [`l1_cache_acs_fail_int_raw::W`](W) writer structure"]
109impl crate::Writable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC {
110    type Safety = crate::Unsafe;
111    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
112    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
113}
114#[doc = "`reset()` method sets L1_CACHE_ACS_FAIL_INT_RAW to value 0"]
115impl crate::Resettable for L1_CACHE_ACS_FAIL_INT_RAW_SPEC {
116    const RESET_VALUE: u32 = 0;
117}
esp32c6/extmem/l1_cache_acs_fail_int_raw.rs

esp32c6/extmem/
l1_cache_acs_fail_int_raw.rs
