esp32c6/dma/in_int_ch/
raw.rs1#[doc = "Register `RAW` reader"]
2pub type R = crate::R<RAW_SPEC>;
3#[doc = "Register `RAW` writer"]
4pub type W = crate::W<RAW_SPEC>;
5#[doc = "Field `IN_DONE` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
6pub type IN_DONE_R = crate::BitReader;
7#[doc = "Field `IN_DONE` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
8pub type IN_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `IN_SUC_EOF` reader - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
10pub type IN_SUC_EOF_R = crate::BitReader;
11#[doc = "Field `IN_SUC_EOF` writer - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
12pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `IN_ERR_EOF` reader - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
14pub type IN_ERR_EOF_R = crate::BitReader;
15#[doc = "Field `IN_ERR_EOF` writer - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `IN_DSCR_ERR` reader - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
18pub type IN_DSCR_ERR_R = crate::BitReader;
19#[doc = "Field `IN_DSCR_ERR` writer - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
20pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `IN_DSCR_EMPTY` reader - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
22pub type IN_DSCR_EMPTY_R = crate::BitReader;
23#[doc = "Field `IN_DSCR_EMPTY` writer - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
24pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `INFIFO_OVF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
26pub type INFIFO_OVF_R = crate::BitReader;
27#[doc = "Field `INFIFO_OVF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
28pub type INFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INFIFO_UDF` reader - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
30pub type INFIFO_UDF_R = crate::BitReader;
31#[doc = "Field `INFIFO_UDF` writer - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
32pub type INFIFO_UDF_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
35 #[inline(always)]
36 pub fn in_done(&self) -> IN_DONE_R {
37 IN_DONE_R::new((self.bits & 1) != 0)
38 }
39 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
40 #[inline(always)]
41 pub fn in_suc_eof(&self) -> IN_SUC_EOF_R {
42 IN_SUC_EOF_R::new(((self.bits >> 1) & 1) != 0)
43 }
44 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
45 #[inline(always)]
46 pub fn in_err_eof(&self) -> IN_ERR_EOF_R {
47 IN_ERR_EOF_R::new(((self.bits >> 2) & 1) != 0)
48 }
49 #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
50 #[inline(always)]
51 pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R {
52 IN_DSCR_ERR_R::new(((self.bits >> 3) & 1) != 0)
53 }
54 #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
55 #[inline(always)]
56 pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R {
57 IN_DSCR_EMPTY_R::new(((self.bits >> 4) & 1) != 0)
58 }
59 #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
60 #[inline(always)]
61 pub fn infifo_ovf(&self) -> INFIFO_OVF_R {
62 INFIFO_OVF_R::new(((self.bits >> 5) & 1) != 0)
63 }
64 #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
65 #[inline(always)]
66 pub fn infifo_udf(&self) -> INFIFO_UDF_R {
67 INFIFO_UDF_R::new(((self.bits >> 6) & 1) != 0)
68 }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73 f.debug_struct("RAW")
74 .field("in_done", &self.in_done())
75 .field("in_suc_eof", &self.in_suc_eof())
76 .field("in_err_eof", &self.in_err_eof())
77 .field("in_dscr_err", &self.in_dscr_err())
78 .field("in_dscr_empty", &self.in_dscr_empty())
79 .field("infifo_ovf", &self.infifo_ovf())
80 .field("infifo_udf", &self.infifo_udf())
81 .finish()
82 }
83}
84impl W {
85 #[doc = "Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0."]
86 #[inline(always)]
87 pub fn in_done(&mut self) -> IN_DONE_W<RAW_SPEC> {
88 IN_DONE_W::new(self, 0)
89 }
90 #[doc = "Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0."]
91 #[inline(always)]
92 pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<RAW_SPEC> {
93 IN_SUC_EOF_W::new(self, 1)
94 }
95 #[doc = "Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved."]
96 #[inline(always)]
97 pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<RAW_SPEC> {
98 IN_ERR_EOF_W::new(self, 2)
99 }
100 #[doc = "Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0."]
101 #[inline(always)]
102 pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<RAW_SPEC> {
103 IN_DSCR_ERR_W::new(self, 3)
104 }
105 #[doc = "Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0."]
106 #[inline(always)]
107 pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<RAW_SPEC> {
108 IN_DSCR_EMPTY_W::new(self, 4)
109 }
110 #[doc = "Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow."]
111 #[inline(always)]
112 pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<RAW_SPEC> {
113 INFIFO_OVF_W::new(self, 5)
114 }
115 #[doc = "Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow."]
116 #[inline(always)]
117 pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<RAW_SPEC> {
118 INFIFO_UDF_W::new(self, 6)
119 }
120}
121#[doc = "Raw status interrupt of channel 0\n\nYou can [`read`](crate::Reg::read) this register and get [`raw::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`raw::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct RAW_SPEC;
123impl crate::RegisterSpec for RAW_SPEC {
124 type Ux = u32;
125}
126#[doc = "`read()` method returns [`raw::R`](R) reader structure"]
127impl crate::Readable for RAW_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`raw::W`](W) writer structure"]
129impl crate::Writable for RAW_SPEC {
130 type Safety = crate::Unsafe;
131 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
132 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
133}
134#[doc = "`reset()` method sets RAW to value 0"]
135impl crate::Resettable for RAW_SPEC {
136 const RESET_VALUE: u32 = 0;
137}