esp32c6/apb_saradc/
filter_ctrl0.rs

1#[doc = "Register `FILTER_CTRL0` reader"]
2pub type R = crate::R<FILTER_CTRL0_SPEC>;
3#[doc = "Register `FILTER_CTRL0` writer"]
4pub type W = crate::W<FILTER_CTRL0_SPEC>;
5#[doc = "Field `FILTER_CHANNEL1` reader - configure filter1 to adc channel"]
6pub type FILTER_CHANNEL1_R = crate::FieldReader;
7#[doc = "Field `FILTER_CHANNEL1` writer - configure filter1 to adc channel"]
8pub type FILTER_CHANNEL1_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `FILTER_CHANNEL0` reader - configure filter0 to adc channel"]
10pub type FILTER_CHANNEL0_R = crate::FieldReader;
11#[doc = "Field `FILTER_CHANNEL0` writer - configure filter0 to adc channel"]
12pub type FILTER_CHANNEL0_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `FILTER_RESET` reader - enable apb_adc1_filter"]
14pub type FILTER_RESET_R = crate::BitReader;
15#[doc = "Field `FILTER_RESET` writer - enable apb_adc1_filter"]
16pub type FILTER_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 18:21 - configure filter1 to adc channel"]
19    #[inline(always)]
20    pub fn filter_channel1(&self) -> FILTER_CHANNEL1_R {
21        FILTER_CHANNEL1_R::new(((self.bits >> 18) & 0x0f) as u8)
22    }
23    #[doc = "Bits 22:25 - configure filter0 to adc channel"]
24    #[inline(always)]
25    pub fn filter_channel0(&self) -> FILTER_CHANNEL0_R {
26        FILTER_CHANNEL0_R::new(((self.bits >> 22) & 0x0f) as u8)
27    }
28    #[doc = "Bit 31 - enable apb_adc1_filter"]
29    #[inline(always)]
30    pub fn filter_reset(&self) -> FILTER_RESET_R {
31        FILTER_RESET_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("FILTER_CTRL0")
38            .field("filter_channel1", &self.filter_channel1())
39            .field("filter_channel0", &self.filter_channel0())
40            .field("filter_reset", &self.filter_reset())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 18:21 - configure filter1 to adc channel"]
46    #[inline(always)]
47    pub fn filter_channel1(&mut self) -> FILTER_CHANNEL1_W<FILTER_CTRL0_SPEC> {
48        FILTER_CHANNEL1_W::new(self, 18)
49    }
50    #[doc = "Bits 22:25 - configure filter0 to adc channel"]
51    #[inline(always)]
52    pub fn filter_channel0(&mut self) -> FILTER_CHANNEL0_W<FILTER_CTRL0_SPEC> {
53        FILTER_CHANNEL0_W::new(self, 22)
54    }
55    #[doc = "Bit 31 - enable apb_adc1_filter"]
56    #[inline(always)]
57    pub fn filter_reset(&mut self) -> FILTER_RESET_W<FILTER_CTRL0_SPEC> {
58        FILTER_RESET_W::new(self, 31)
59    }
60}
61#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`filter_ctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`filter_ctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct FILTER_CTRL0_SPEC;
63impl crate::RegisterSpec for FILTER_CTRL0_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`filter_ctrl0::R`](R) reader structure"]
67impl crate::Readable for FILTER_CTRL0_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`filter_ctrl0::W`](W) writer structure"]
69impl crate::Writable for FILTER_CTRL0_SPEC {
70    type Safety = crate::Unsafe;
71    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
73}
74#[doc = "`reset()` method sets FILTER_CTRL0 to value 0x0374_0000"]
75impl crate::Resettable for FILTER_CTRL0_SPEC {
76    const RESET_VALUE: u32 = 0x0374_0000;
77}
esp32c6/apb_saradc/filter_ctrl0.rs

esp32c6/apb_saradc/
filter_ctrl0.rs
