esp32c6_lp/pmu/
power_vdd_spi_cntl.rs

1#[doc = "Register `POWER_VDD_SPI_CNTL` reader"]
2pub type R = crate::R<POWER_VDD_SPI_CNTL_SPEC>;
3#[doc = "Register `POWER_VDD_SPI_CNTL` writer"]
4pub type W = crate::W<POWER_VDD_SPI_CNTL_SPEC>;
5#[doc = "Field `VDD_SPI_PWR_WAIT` reader - need_des"]
6pub type VDD_SPI_PWR_WAIT_R = crate::FieldReader<u16>;
7#[doc = "Field `VDD_SPI_PWR_WAIT` writer - need_des"]
8pub type VDD_SPI_PWR_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9#[doc = "Field `VDD_SPI_PWR_SW` reader - need_des"]
10pub type VDD_SPI_PWR_SW_R = crate::FieldReader;
11#[doc = "Field `VDD_SPI_PWR_SW` writer - need_des"]
12pub type VDD_SPI_PWR_SW_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `VDD_SPI_PWR_SEL_SW` reader - need_des"]
14pub type VDD_SPI_PWR_SEL_SW_R = crate::BitReader;
15#[doc = "Field `VDD_SPI_PWR_SEL_SW` writer - need_des"]
16pub type VDD_SPI_PWR_SEL_SW_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 18:28 - need_des"]
19    #[inline(always)]
20    pub fn vdd_spi_pwr_wait(&self) -> VDD_SPI_PWR_WAIT_R {
21        VDD_SPI_PWR_WAIT_R::new(((self.bits >> 18) & 0x07ff) as u16)
22    }
23    #[doc = "Bits 29:30 - need_des"]
24    #[inline(always)]
25    pub fn vdd_spi_pwr_sw(&self) -> VDD_SPI_PWR_SW_R {
26        VDD_SPI_PWR_SW_R::new(((self.bits >> 29) & 3) as u8)
27    }
28    #[doc = "Bit 31 - need_des"]
29    #[inline(always)]
30    pub fn vdd_spi_pwr_sel_sw(&self) -> VDD_SPI_PWR_SEL_SW_R {
31        VDD_SPI_PWR_SEL_SW_R::new(((self.bits >> 31) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("POWER_VDD_SPI_CNTL")
38            .field("vdd_spi_pwr_wait", &self.vdd_spi_pwr_wait())
39            .field("vdd_spi_pwr_sw", &self.vdd_spi_pwr_sw())
40            .field("vdd_spi_pwr_sel_sw", &self.vdd_spi_pwr_sel_sw())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 18:28 - need_des"]
46    #[inline(always)]
47    #[must_use]
48    pub fn vdd_spi_pwr_wait(&mut self) -> VDD_SPI_PWR_WAIT_W<POWER_VDD_SPI_CNTL_SPEC> {
49        VDD_SPI_PWR_WAIT_W::new(self, 18)
50    }
51    #[doc = "Bits 29:30 - need_des"]
52    #[inline(always)]
53    #[must_use]
54    pub fn vdd_spi_pwr_sw(&mut self) -> VDD_SPI_PWR_SW_W<POWER_VDD_SPI_CNTL_SPEC> {
55        VDD_SPI_PWR_SW_W::new(self, 29)
56    }
57    #[doc = "Bit 31 - need_des"]
58    #[inline(always)]
59    #[must_use]
60    pub fn vdd_spi_pwr_sel_sw(&mut self) -> VDD_SPI_PWR_SEL_SW_W<POWER_VDD_SPI_CNTL_SPEC> {
61        VDD_SPI_PWR_SEL_SW_W::new(self, 31)
62    }
63}
64#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`power_vdd_spi_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`power_vdd_spi_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct POWER_VDD_SPI_CNTL_SPEC;
66impl crate::RegisterSpec for POWER_VDD_SPI_CNTL_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`power_vdd_spi_cntl::R`](R) reader structure"]
70impl crate::Readable for POWER_VDD_SPI_CNTL_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`power_vdd_spi_cntl::W`](W) writer structure"]
72impl crate::Writable for POWER_VDD_SPI_CNTL_SPEC {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77#[doc = "`reset()` method sets POWER_VDD_SPI_CNTL to value 0x63fc_0000"]
78impl crate::Resettable for POWER_VDD_SPI_CNTL_SPEC {
79    const RESET_VALUE: u32 = 0x63fc_0000;
80}
esp32c6_lp/pmu/power_vdd_spi_cntl.rs

esp32c6_lp/pmu/
power_vdd_spi_cntl.rs
