esp32c6_lp/pmu/
power_ck_wait_cntl.rs

1#[doc = "Register `POWER_CK_WAIT_CNTL` reader"]
2pub type R = crate::R<POWER_CK_WAIT_CNTL_SPEC>;
3#[doc = "Register `POWER_CK_WAIT_CNTL` writer"]
4pub type W = crate::W<POWER_CK_WAIT_CNTL_SPEC>;
5#[doc = "Field `WAIT_XTL_STABLE` reader - need_des"]
6pub type WAIT_XTL_STABLE_R = crate::FieldReader<u16>;
7#[doc = "Field `WAIT_XTL_STABLE` writer - need_des"]
8pub type WAIT_XTL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `WAIT_PLL_STABLE` reader - need_des"]
10pub type WAIT_PLL_STABLE_R = crate::FieldReader<u16>;
11#[doc = "Field `WAIT_PLL_STABLE` writer - need_des"]
12pub type WAIT_PLL_STABLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - need_des"]
15    #[inline(always)]
16    pub fn wait_xtl_stable(&self) -> WAIT_XTL_STABLE_R {
17        WAIT_XTL_STABLE_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - need_des"]
20    #[inline(always)]
21    pub fn wait_pll_stable(&self) -> WAIT_PLL_STABLE_R {
22        WAIT_PLL_STABLE_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("POWER_CK_WAIT_CNTL")
29            .field("wait_xtl_stable", &self.wait_xtl_stable())
30            .field("wait_pll_stable", &self.wait_pll_stable())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - need_des"]
36    #[inline(always)]
37    #[must_use]
38    pub fn wait_xtl_stable(&mut self) -> WAIT_XTL_STABLE_W<POWER_CK_WAIT_CNTL_SPEC> {
39        WAIT_XTL_STABLE_W::new(self, 0)
40    }
41    #[doc = "Bits 16:31 - need_des"]
42    #[inline(always)]
43    #[must_use]
44    pub fn wait_pll_stable(&mut self) -> WAIT_PLL_STABLE_W<POWER_CK_WAIT_CNTL_SPEC> {
45        WAIT_PLL_STABLE_W::new(self, 16)
46    }
47}
48#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`power_ck_wait_cntl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`power_ck_wait_cntl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
49pub struct POWER_CK_WAIT_CNTL_SPEC;
50impl crate::RegisterSpec for POWER_CK_WAIT_CNTL_SPEC {
51    type Ux = u32;
52}
53#[doc = "`read()` method returns [`power_ck_wait_cntl::R`](R) reader structure"]
54impl crate::Readable for POWER_CK_WAIT_CNTL_SPEC {}
55#[doc = "`write(|w| ..)` method takes [`power_ck_wait_cntl::W`](W) writer structure"]
56impl crate::Writable for POWER_CK_WAIT_CNTL_SPEC {
57    type Safety = crate::Unsafe;
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
60}
61#[doc = "`reset()` method sets POWER_CK_WAIT_CNTL to value 0x0100_0100"]
62impl crate::Resettable for POWER_CK_WAIT_CNTL_SPEC {
63    const RESET_VALUE: u32 = 0x0100_0100;
64}
esp32c6_lp/pmu/power_ck_wait_cntl.rs

esp32c6_lp/pmu/
power_ck_wait_cntl.rs
