esp32c6_lp/pmu/
hp_active_sysclk.rs

1#[doc = "Register `HP_ACTIVE_SYSCLK` reader"]
2pub type R = crate::R<HP_ACTIVE_SYSCLK_SPEC>;
3#[doc = "Register `HP_ACTIVE_SYSCLK` writer"]
4pub type W = crate::W<HP_ACTIVE_SYSCLK_SPEC>;
5#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_NO_DIV` reader - need_des"]
6pub type HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R = crate::BitReader;
7#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_NO_DIV` writer - need_des"]
8pub type HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `HP_ACTIVE_ICG_SYS_CLOCK_EN` reader - need_des"]
10pub type HP_ACTIVE_ICG_SYS_CLOCK_EN_R = crate::BitReader;
11#[doc = "Field `HP_ACTIVE_ICG_SYS_CLOCK_EN` writer - need_des"]
12pub type HP_ACTIVE_ICG_SYS_CLOCK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `HP_ACTIVE_SYS_CLK_SLP_SEL` reader - need_des"]
14pub type HP_ACTIVE_SYS_CLK_SLP_SEL_R = crate::BitReader;
15#[doc = "Field `HP_ACTIVE_SYS_CLK_SLP_SEL` writer - need_des"]
16pub type HP_ACTIVE_SYS_CLK_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `HP_ACTIVE_ICG_SLP_SEL` reader - need_des"]
18pub type HP_ACTIVE_ICG_SLP_SEL_R = crate::BitReader;
19#[doc = "Field `HP_ACTIVE_ICG_SLP_SEL` writer - need_des"]
20pub type HP_ACTIVE_ICG_SLP_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_SEL` reader - need_des"]
22pub type HP_ACTIVE_DIG_SYS_CLK_SEL_R = crate::FieldReader;
23#[doc = "Field `HP_ACTIVE_DIG_SYS_CLK_SEL` writer - need_des"]
24pub type HP_ACTIVE_DIG_SYS_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26    #[doc = "Bit 26 - need_des"]
27    #[inline(always)]
28    pub fn hp_active_dig_sys_clk_no_div(&self) -> HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R {
29        HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R::new(((self.bits >> 26) & 1) != 0)
30    }
31    #[doc = "Bit 27 - need_des"]
32    #[inline(always)]
33    pub fn hp_active_icg_sys_clock_en(&self) -> HP_ACTIVE_ICG_SYS_CLOCK_EN_R {
34        HP_ACTIVE_ICG_SYS_CLOCK_EN_R::new(((self.bits >> 27) & 1) != 0)
35    }
36    #[doc = "Bit 28 - need_des"]
37    #[inline(always)]
38    pub fn hp_active_sys_clk_slp_sel(&self) -> HP_ACTIVE_SYS_CLK_SLP_SEL_R {
39        HP_ACTIVE_SYS_CLK_SLP_SEL_R::new(((self.bits >> 28) & 1) != 0)
40    }
41    #[doc = "Bit 29 - need_des"]
42    #[inline(always)]
43    pub fn hp_active_icg_slp_sel(&self) -> HP_ACTIVE_ICG_SLP_SEL_R {
44        HP_ACTIVE_ICG_SLP_SEL_R::new(((self.bits >> 29) & 1) != 0)
45    }
46    #[doc = "Bits 30:31 - need_des"]
47    #[inline(always)]
48    pub fn hp_active_dig_sys_clk_sel(&self) -> HP_ACTIVE_DIG_SYS_CLK_SEL_R {
49        HP_ACTIVE_DIG_SYS_CLK_SEL_R::new(((self.bits >> 30) & 3) as u8)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("HP_ACTIVE_SYSCLK")
56            .field(
57                "hp_active_dig_sys_clk_no_div",
58                &self.hp_active_dig_sys_clk_no_div(),
59            )
60            .field(
61                "hp_active_icg_sys_clock_en",
62                &self.hp_active_icg_sys_clock_en(),
63            )
64            .field(
65                "hp_active_sys_clk_slp_sel",
66                &self.hp_active_sys_clk_slp_sel(),
67            )
68            .field("hp_active_icg_slp_sel", &self.hp_active_icg_slp_sel())
69            .field(
70                "hp_active_dig_sys_clk_sel",
71                &self.hp_active_dig_sys_clk_sel(),
72            )
73            .finish()
74    }
75}
76impl W {
77    #[doc = "Bit 26 - need_des"]
78    #[inline(always)]
79    #[must_use]
80    pub fn hp_active_dig_sys_clk_no_div(
81        &mut self,
82    ) -> HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W<HP_ACTIVE_SYSCLK_SPEC> {
83        HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W::new(self, 26)
84    }
85    #[doc = "Bit 27 - need_des"]
86    #[inline(always)]
87    #[must_use]
88    pub fn hp_active_icg_sys_clock_en(
89        &mut self,
90    ) -> HP_ACTIVE_ICG_SYS_CLOCK_EN_W<HP_ACTIVE_SYSCLK_SPEC> {
91        HP_ACTIVE_ICG_SYS_CLOCK_EN_W::new(self, 27)
92    }
93    #[doc = "Bit 28 - need_des"]
94    #[inline(always)]
95    #[must_use]
96    pub fn hp_active_sys_clk_slp_sel(
97        &mut self,
98    ) -> HP_ACTIVE_SYS_CLK_SLP_SEL_W<HP_ACTIVE_SYSCLK_SPEC> {
99        HP_ACTIVE_SYS_CLK_SLP_SEL_W::new(self, 28)
100    }
101    #[doc = "Bit 29 - need_des"]
102    #[inline(always)]
103    #[must_use]
104    pub fn hp_active_icg_slp_sel(&mut self) -> HP_ACTIVE_ICG_SLP_SEL_W<HP_ACTIVE_SYSCLK_SPEC> {
105        HP_ACTIVE_ICG_SLP_SEL_W::new(self, 29)
106    }
107    #[doc = "Bits 30:31 - need_des"]
108    #[inline(always)]
109    #[must_use]
110    pub fn hp_active_dig_sys_clk_sel(
111        &mut self,
112    ) -> HP_ACTIVE_DIG_SYS_CLK_SEL_W<HP_ACTIVE_SYSCLK_SPEC> {
113        HP_ACTIVE_DIG_SYS_CLK_SEL_W::new(self, 30)
114    }
115}
116#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`hp_active_sysclk::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hp_active_sysclk::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
117pub struct HP_ACTIVE_SYSCLK_SPEC;
118impl crate::RegisterSpec for HP_ACTIVE_SYSCLK_SPEC {
119    type Ux = u32;
120}
121#[doc = "`read()` method returns [`hp_active_sysclk::R`](R) reader structure"]
122impl crate::Readable for HP_ACTIVE_SYSCLK_SPEC {}
123#[doc = "`write(|w| ..)` method takes [`hp_active_sysclk::W`](W) writer structure"]
124impl crate::Writable for HP_ACTIVE_SYSCLK_SPEC {
125    type Safety = crate::Unsafe;
126    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
127    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
128}
129#[doc = "`reset()` method sets HP_ACTIVE_SYSCLK to value 0"]
130impl crate::Resettable for HP_ACTIVE_SYSCLK_SPEC {
131    const RESET_VALUE: u32 = 0;
132}
esp32c6_lp/pmu/hp_active_sysclk.rs

esp32c6_lp/pmu/
hp_active_sysclk.rs
