esp32c6_lp/lp_uart/
rx_filt.rs

1#[doc = "Register `RX_FILT` reader"]
2pub type R = crate::R<RX_FILT_SPEC>;
3#[doc = "Register `RX_FILT` writer"]
4pub type W = crate::W<RX_FILT_SPEC>;
5#[doc = "Field `GLITCH_FILT` reader - when input pulse width is lower than this value the pulse is ignored."]
6pub type GLITCH_FILT_R = crate::FieldReader;
7#[doc = "Field `GLITCH_FILT` writer - when input pulse width is lower than this value the pulse is ignored."]
8pub type GLITCH_FILT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `GLITCH_FILT_EN` reader - Set this bit to enable Rx signal filter."]
10pub type GLITCH_FILT_EN_R = crate::BitReader;
11#[doc = "Field `GLITCH_FILT_EN` writer - Set this bit to enable Rx signal filter."]
12pub type GLITCH_FILT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
15    #[inline(always)]
16    pub fn glitch_filt(&self) -> GLITCH_FILT_R {
17        GLITCH_FILT_R::new((self.bits & 0xff) as u8)
18    }
19    #[doc = "Bit 8 - Set this bit to enable Rx signal filter."]
20    #[inline(always)]
21    pub fn glitch_filt_en(&self) -> GLITCH_FILT_EN_R {
22        GLITCH_FILT_EN_R::new(((self.bits >> 8) & 1) != 0)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("RX_FILT")
29            .field("glitch_filt", &self.glitch_filt())
30            .field("glitch_filt_en", &self.glitch_filt_en())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:7 - when input pulse width is lower than this value the pulse is ignored."]
36    #[inline(always)]
37    #[must_use]
38    pub fn glitch_filt(&mut self) -> GLITCH_FILT_W<RX_FILT_SPEC> {
39        GLITCH_FILT_W::new(self, 0)
40    }
41    #[doc = "Bit 8 - Set this bit to enable Rx signal filter."]
42    #[inline(always)]
43    #[must_use]
44    pub fn glitch_filt_en(&mut self) -> GLITCH_FILT_EN_W<RX_FILT_SPEC> {
45        GLITCH_FILT_EN_W::new(self, 8)
46    }
47}
48#[doc = "Rx Filter configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_filt::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rx_filt::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
49pub struct RX_FILT_SPEC;
50impl crate::RegisterSpec for RX_FILT_SPEC {
51    type Ux = u32;
52}
53#[doc = "`read()` method returns [`rx_filt::R`](R) reader structure"]
54impl crate::Readable for RX_FILT_SPEC {}
55#[doc = "`write(|w| ..)` method takes [`rx_filt::W`](W) writer structure"]
56impl crate::Writable for RX_FILT_SPEC {
57    type Safety = crate::Unsafe;
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
60}
61#[doc = "`reset()` method sets RX_FILT to value 0x08"]
62impl crate::Resettable for RX_FILT_SPEC {
63    const RESET_VALUE: u32 = 0x08;
64}
esp32c6_lp/lp_uart/rx_filt.rs

esp32c6_lp/lp_uart/
rx_filt.rs
