esp32c6_lp/lp_uart/
conf0_sync.rs

1#[doc = "Register `CONF0_SYNC` reader"]
2pub type R = crate::R<CONF0_SYNC_SPEC>;
3#[doc = "Register `CONF0_SYNC` writer"]
4pub type W = crate::W<CONF0_SYNC_SPEC>;
5#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."]
6pub type PARITY_R = crate::BitReader;
7#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."]
8pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."]
10pub type PARITY_EN_R = crate::BitReader;
11#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."]
12pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."]
14pub type BIT_NUM_R = crate::FieldReader;
15#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."]
16pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."]
18pub type STOP_BIT_NUM_R = crate::FieldReader;
19#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."]
20pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
22pub type TXD_BRK_R = crate::BitReader;
23#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
24pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."]
26pub type LOOPBACK_R = crate::BitReader;
27#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."]
28pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."]
30pub type TX_FLOW_EN_R = crate::BitReader;
31#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."]
32pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."]
34pub type RXD_INV_R = crate::BitReader;
35#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."]
36pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."]
38pub type TXD_INV_R = crate::BitReader;
39#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."]
40pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DIS_RX_DAT_OVF` reader - Disable UART Rx data overflow detect."]
42pub type DIS_RX_DAT_OVF_R = crate::BitReader;
43#[doc = "Field `DIS_RX_DAT_OVF` writer - Disable UART Rx data overflow detect."]
44pub type DIS_RX_DAT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
46pub type ERR_WR_MASK_R = crate::BitReader;
47#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
48pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."]
50pub type MEM_CLK_EN_R = crate::BitReader;
51#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."]
52pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."]
54pub type SW_RTS_R = crate::BitReader;
55#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."]
56pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."]
58pub type RXFIFO_RST_R = crate::BitReader;
59#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."]
60pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."]
62pub type TXFIFO_RST_R = crate::BitReader;
63#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."]
64pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66    #[doc = "Bit 0 - This register is used to configure the parity check mode."]
67    #[inline(always)]
68    pub fn parity(&self) -> PARITY_R {
69        PARITY_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Set this bit to enable uart parity check."]
72    #[inline(always)]
73    pub fn parity_en(&self) -> PARITY_EN_R {
74        PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bits 2:3 - This register is used to set the length of data."]
77    #[inline(always)]
78    pub fn bit_num(&self) -> BIT_NUM_R {
79        BIT_NUM_R::new(((self.bits >> 2) & 3) as u8)
80    }
81    #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
82    #[inline(always)]
83    pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R {
84        STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8)
85    }
86    #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
87    #[inline(always)]
88    pub fn txd_brk(&self) -> TXD_BRK_R {
89        TXD_BRK_R::new(((self.bits >> 6) & 1) != 0)
90    }
91    #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
92    #[inline(always)]
93    pub fn loopback(&self) -> LOOPBACK_R {
94        LOOPBACK_R::new(((self.bits >> 12) & 1) != 0)
95    }
96    #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
97    #[inline(always)]
98    pub fn tx_flow_en(&self) -> TX_FLOW_EN_R {
99        TX_FLOW_EN_R::new(((self.bits >> 13) & 1) != 0)
100    }
101    #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
102    #[inline(always)]
103    pub fn rxd_inv(&self) -> RXD_INV_R {
104        RXD_INV_R::new(((self.bits >> 15) & 1) != 0)
105    }
106    #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
107    #[inline(always)]
108    pub fn txd_inv(&self) -> TXD_INV_R {
109        TXD_INV_R::new(((self.bits >> 16) & 1) != 0)
110    }
111    #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
112    #[inline(always)]
113    pub fn dis_rx_dat_ovf(&self) -> DIS_RX_DAT_OVF_R {
114        DIS_RX_DAT_OVF_R::new(((self.bits >> 17) & 1) != 0)
115    }
116    #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
117    #[inline(always)]
118    pub fn err_wr_mask(&self) -> ERR_WR_MASK_R {
119        ERR_WR_MASK_R::new(((self.bits >> 18) & 1) != 0)
120    }
121    #[doc = "Bit 20 - UART memory clock gate enable signal."]
122    #[inline(always)]
123    pub fn mem_clk_en(&self) -> MEM_CLK_EN_R {
124        MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
125    }
126    #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
127    #[inline(always)]
128    pub fn sw_rts(&self) -> SW_RTS_R {
129        SW_RTS_R::new(((self.bits >> 21) & 1) != 0)
130    }
131    #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
132    #[inline(always)]
133    pub fn rxfifo_rst(&self) -> RXFIFO_RST_R {
134        RXFIFO_RST_R::new(((self.bits >> 22) & 1) != 0)
135    }
136    #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
137    #[inline(always)]
138    pub fn txfifo_rst(&self) -> TXFIFO_RST_R {
139        TXFIFO_RST_R::new(((self.bits >> 23) & 1) != 0)
140    }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145        f.debug_struct("CONF0_SYNC")
146            .field("parity", &self.parity())
147            .field("parity_en", &self.parity_en())
148            .field("bit_num", &self.bit_num())
149            .field("stop_bit_num", &self.stop_bit_num())
150            .field("txd_brk", &self.txd_brk())
151            .field("loopback", &self.loopback())
152            .field("tx_flow_en", &self.tx_flow_en())
153            .field("rxd_inv", &self.rxd_inv())
154            .field("txd_inv", &self.txd_inv())
155            .field("dis_rx_dat_ovf", &self.dis_rx_dat_ovf())
156            .field("err_wr_mask", &self.err_wr_mask())
157            .field("mem_clk_en", &self.mem_clk_en())
158            .field("sw_rts", &self.sw_rts())
159            .field("rxfifo_rst", &self.rxfifo_rst())
160            .field("txfifo_rst", &self.txfifo_rst())
161            .finish()
162    }
163}
164impl W {
165    #[doc = "Bit 0 - This register is used to configure the parity check mode."]
166    #[inline(always)]
167    #[must_use]
168    pub fn parity(&mut self) -> PARITY_W<CONF0_SYNC_SPEC> {
169        PARITY_W::new(self, 0)
170    }
171    #[doc = "Bit 1 - Set this bit to enable uart parity check."]
172    #[inline(always)]
173    #[must_use]
174    pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SYNC_SPEC> {
175        PARITY_EN_W::new(self, 1)
176    }
177    #[doc = "Bits 2:3 - This register is used to set the length of data."]
178    #[inline(always)]
179    #[must_use]
180    pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SYNC_SPEC> {
181        BIT_NUM_W::new(self, 2)
182    }
183    #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
184    #[inline(always)]
185    #[must_use]
186    pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SYNC_SPEC> {
187        STOP_BIT_NUM_W::new(self, 4)
188    }
189    #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
190    #[inline(always)]
191    #[must_use]
192    pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SYNC_SPEC> {
193        TXD_BRK_W::new(self, 6)
194    }
195    #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
196    #[inline(always)]
197    #[must_use]
198    pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SYNC_SPEC> {
199        LOOPBACK_W::new(self, 12)
200    }
201    #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
202    #[inline(always)]
203    #[must_use]
204    pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SYNC_SPEC> {
205        TX_FLOW_EN_W::new(self, 13)
206    }
207    #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
208    #[inline(always)]
209    #[must_use]
210    pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SYNC_SPEC> {
211        RXD_INV_W::new(self, 15)
212    }
213    #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
214    #[inline(always)]
215    #[must_use]
216    pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SYNC_SPEC> {
217        TXD_INV_W::new(self, 16)
218    }
219    #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
220    #[inline(always)]
221    #[must_use]
222    pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W<CONF0_SYNC_SPEC> {
223        DIS_RX_DAT_OVF_W::new(self, 17)
224    }
225    #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
226    #[inline(always)]
227    #[must_use]
228    pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SYNC_SPEC> {
229        ERR_WR_MASK_W::new(self, 18)
230    }
231    #[doc = "Bit 20 - UART memory clock gate enable signal."]
232    #[inline(always)]
233    #[must_use]
234    pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SYNC_SPEC> {
235        MEM_CLK_EN_W::new(self, 20)
236    }
237    #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
238    #[inline(always)]
239    #[must_use]
240    pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SYNC_SPEC> {
241        SW_RTS_W::new(self, 21)
242    }
243    #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
244    #[inline(always)]
245    #[must_use]
246    pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SYNC_SPEC> {
247        RXFIFO_RST_W::new(self, 22)
248    }
249    #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
250    #[inline(always)]
251    #[must_use]
252    pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SYNC_SPEC> {
253        TXFIFO_RST_W::new(self, 23)
254    }
255}
256#[doc = "Configuration register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct CONF0_SYNC_SPEC;
258impl crate::RegisterSpec for CONF0_SYNC_SPEC {
259    type Ux = u32;
260}
261#[doc = "`read()` method returns [`conf0_sync::R`](R) reader structure"]
262impl crate::Readable for CONF0_SYNC_SPEC {}
263#[doc = "`write(|w| ..)` method takes [`conf0_sync::W`](W) writer structure"]
264impl crate::Writable for CONF0_SYNC_SPEC {
265    type Safety = crate::Unsafe;
266    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
267    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
268}
269#[doc = "`reset()` method sets CONF0_SYNC to value 0x0010_001c"]
270impl crate::Resettable for CONF0_SYNC_SPEC {
271    const RESET_VALUE: u32 = 0x0010_001c;
272}
esp32c6_lp/lp_uart/conf0_sync.rs

esp32c6_lp/lp_uart/
conf0_sync.rs
