esp32c6_lp/lp_i2c0/
scl_sp_conf.rs

1#[doc = "Register `SCL_SP_CONF` reader"]
2pub type R = crate::R<SCL_SP_CONF_SPEC>;
3#[doc = "Register `SCL_SP_CONF` writer"]
4pub type W = crate::W<SCL_SP_CONF_SPEC>;
5#[doc = "Field `SCL_RST_SLV_EN` reader - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
6pub type SCL_RST_SLV_EN_R = crate::BitReader;
7#[doc = "Field `SCL_RST_SLV_EN` writer - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
8pub type SCL_RST_SLV_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_RST_SLV_NUM` reader - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."]
10pub type SCL_RST_SLV_NUM_R = crate::FieldReader;
11#[doc = "Field `SCL_RST_SLV_NUM` writer - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."]
12pub type SCL_RST_SLV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `SCL_PD_EN` reader - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."]
14pub type SCL_PD_EN_R = crate::BitReader;
15#[doc = "Field `SCL_PD_EN` writer - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."]
16pub type SCL_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SDA_PD_EN` reader - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."]
18pub type SDA_PD_EN_R = crate::BitReader;
19#[doc = "Field `SDA_PD_EN` writer - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."]
20pub type SDA_PD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
23    #[inline(always)]
24    pub fn scl_rst_slv_en(&self) -> SCL_RST_SLV_EN_R {
25        SCL_RST_SLV_EN_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."]
28    #[inline(always)]
29    pub fn scl_rst_slv_num(&self) -> SCL_RST_SLV_NUM_R {
30        SCL_RST_SLV_NUM_R::new(((self.bits >> 1) & 0x1f) as u8)
31    }
32    #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."]
33    #[inline(always)]
34    pub fn scl_pd_en(&self) -> SCL_PD_EN_R {
35        SCL_PD_EN_R::new(((self.bits >> 6) & 1) != 0)
36    }
37    #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."]
38    #[inline(always)]
39    pub fn sda_pd_en(&self) -> SDA_PD_EN_R {
40        SDA_PD_EN_R::new(((self.bits >> 7) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("SCL_SP_CONF")
47            .field("scl_rst_slv_en", &self.scl_rst_slv_en())
48            .field("scl_rst_slv_num", &self.scl_rst_slv_num())
49            .field("scl_pd_en", &self.scl_pd_en())
50            .field("sda_pd_en", &self.sda_pd_en())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0 - When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num\\[4:0\\]."]
56    #[inline(always)]
57    #[must_use]
58    pub fn scl_rst_slv_en(&mut self) -> SCL_RST_SLV_EN_W<SCL_SP_CONF_SPEC> {
59        SCL_RST_SLV_EN_W::new(self, 0)
60    }
61    #[doc = "Bits 1:5 - Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1."]
62    #[inline(always)]
63    #[must_use]
64    pub fn scl_rst_slv_num(&mut self) -> SCL_RST_SLV_NUM_W<SCL_SP_CONF_SPEC> {
65        SCL_RST_SLV_NUM_W::new(self, 1)
66    }
67    #[doc = "Bit 6 - The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low."]
68    #[inline(always)]
69    #[must_use]
70    pub fn scl_pd_en(&mut self) -> SCL_PD_EN_W<SCL_SP_CONF_SPEC> {
71        SCL_PD_EN_W::new(self, 6)
72    }
73    #[doc = "Bit 7 - The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low."]
74    #[inline(always)]
75    #[must_use]
76    pub fn sda_pd_en(&mut self) -> SDA_PD_EN_W<SCL_SP_CONF_SPEC> {
77        SDA_PD_EN_W::new(self, 7)
78    }
79}
80#[doc = "Power configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_sp_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_sp_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
81pub struct SCL_SP_CONF_SPEC;
82impl crate::RegisterSpec for SCL_SP_CONF_SPEC {
83    type Ux = u32;
84}
85#[doc = "`read()` method returns [`scl_sp_conf::R`](R) reader structure"]
86impl crate::Readable for SCL_SP_CONF_SPEC {}
87#[doc = "`write(|w| ..)` method takes [`scl_sp_conf::W`](W) writer structure"]
88impl crate::Writable for SCL_SP_CONF_SPEC {
89    type Safety = crate::Unsafe;
90    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92}
93#[doc = "`reset()` method sets SCL_SP_CONF to value 0"]
94impl crate::Resettable for SCL_SP_CONF_SPEC {
95    const RESET_VALUE: u32 = 0;
96}
esp32c6_lp/lp_i2c0/scl_sp_conf.rs

esp32c6_lp/lp_i2c0/
scl_sp_conf.rs
