esp32c6_lp/lp_i2c0/
scl_high_period.rs

1#[doc = "Register `SCL_HIGH_PERIOD` reader"]
2pub type R = crate::R<SCL_HIGH_PERIOD_SPEC>;
3#[doc = "Register `SCL_HIGH_PERIOD` writer"]
4pub type W = crate::W<SCL_HIGH_PERIOD_SPEC>;
5#[doc = "Field `SCL_HIGH_PERIOD` reader - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
6pub type SCL_HIGH_PERIOD_R = crate::FieldReader<u16>;
7#[doc = "Field `SCL_HIGH_PERIOD` writer - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
8pub type SCL_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 9, u16>;
9#[doc = "Field `SCL_WAIT_HIGH_PERIOD` reader - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."]
10pub type SCL_WAIT_HIGH_PERIOD_R = crate::FieldReader;
11#[doc = "Field `SCL_WAIT_HIGH_PERIOD` writer - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."]
12pub type SCL_WAIT_HIGH_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
13impl R {
14    #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
15    #[inline(always)]
16    pub fn scl_high_period(&self) -> SCL_HIGH_PERIOD_R {
17        SCL_HIGH_PERIOD_R::new((self.bits & 0x01ff) as u16)
18    }
19    #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."]
20    #[inline(always)]
21    pub fn scl_wait_high_period(&self) -> SCL_WAIT_HIGH_PERIOD_R {
22        SCL_WAIT_HIGH_PERIOD_R::new(((self.bits >> 9) & 0x7f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("SCL_HIGH_PERIOD")
29            .field("scl_high_period", &self.scl_high_period())
30            .field("scl_wait_high_period", &self.scl_wait_high_period())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:8 - This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles."]
36    #[inline(always)]
37    #[must_use]
38    pub fn scl_high_period(&mut self) -> SCL_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
39        SCL_HIGH_PERIOD_W::new(self, 0)
40    }
41    #[doc = "Bits 9:15 - This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles."]
42    #[inline(always)]
43    #[must_use]
44    pub fn scl_wait_high_period(&mut self) -> SCL_WAIT_HIGH_PERIOD_W<SCL_HIGH_PERIOD_SPEC> {
45        SCL_WAIT_HIGH_PERIOD_W::new(self, 9)
46    }
47}
48#[doc = "Configures the high level width of SCL\n\nYou can [`read`](crate::Reg::read) this register and get [`scl_high_period::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`scl_high_period::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
49pub struct SCL_HIGH_PERIOD_SPEC;
50impl crate::RegisterSpec for SCL_HIGH_PERIOD_SPEC {
51    type Ux = u32;
52}
53#[doc = "`read()` method returns [`scl_high_period::R`](R) reader structure"]
54impl crate::Readable for SCL_HIGH_PERIOD_SPEC {}
55#[doc = "`write(|w| ..)` method takes [`scl_high_period::W`](W) writer structure"]
56impl crate::Writable for SCL_HIGH_PERIOD_SPEC {
57    type Safety = crate::Unsafe;
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
60}
61#[doc = "`reset()` method sets SCL_HIGH_PERIOD to value 0"]
62impl crate::Resettable for SCL_HIGH_PERIOD_SPEC {
63    const RESET_VALUE: u32 = 0;
64}
esp32c6_lp/lp_i2c0/scl_high_period.rs

esp32c6_lp/lp_i2c0/
scl_high_period.rs
