esp32c6_lp/lp_i2c0/
ctr.rs1#[doc = "Register `CTR` reader"]
2pub type R = crate::R<CTR_SPEC>;
3#[doc = "Register `CTR` writer"]
4pub type W = crate::W<CTR_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - 1: direct output, 0: open drain output."]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - 1: direct output, 0: open drain output."]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - 1: direct output, 0: open drain output."]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - 1: direct output, 0: open drain output."]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SAMPLE_SCL_LEVEL` reader - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
14pub type SAMPLE_SCL_LEVEL_R = crate::BitReader;
15#[doc = "Field `SAMPLE_SCL_LEVEL` writer - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
16pub type SAMPLE_SCL_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_FULL_ACK_LEVEL` reader - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
18pub type RX_FULL_ACK_LEVEL_R = crate::BitReader;
19#[doc = "Field `RX_FULL_ACK_LEVEL` writer - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
20pub type RX_FULL_ACK_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TRANS_START` writer - Set this bit to start sending the data in txfifo."]
22pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
23#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
24pub type TX_LSB_FIRST_R = crate::BitReader;
25#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
26pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit."]
28pub type RX_LSB_FIRST_R = crate::BitReader;
29#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit."]
30pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `CLK_EN` reader - Reserved"]
32pub type CLK_EN_R = crate::BitReader;
33#[doc = "Field `CLK_EN` writer - Reserved"]
34pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `ARBITRATION_EN` reader - This is the enable bit for arbitration_lost."]
36pub type ARBITRATION_EN_R = crate::BitReader;
37#[doc = "Field `ARBITRATION_EN` writer - This is the enable bit for arbitration_lost."]
38pub type ARBITRATION_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `FSM_RST` writer - This register is used to reset the scl FMS."]
40pub type FSM_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CONF_UPGATE` writer - synchronization bit"]
42pub type CONF_UPGATE_W<'a, REG> = crate::BitWriter<'a, REG>;
43impl R {
44 #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
45 #[inline(always)]
46 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
47 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
48 }
49 #[doc = "Bit 1 - 1: direct output, 0: open drain output."]
50 #[inline(always)]
51 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
52 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
53 }
54 #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
55 #[inline(always)]
56 pub fn sample_scl_level(&self) -> SAMPLE_SCL_LEVEL_R {
57 SAMPLE_SCL_LEVEL_R::new(((self.bits >> 2) & 1) != 0)
58 }
59 #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
60 #[inline(always)]
61 pub fn rx_full_ack_level(&self) -> RX_FULL_ACK_LEVEL_R {
62 RX_FULL_ACK_LEVEL_R::new(((self.bits >> 3) & 1) != 0)
63 }
64 #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
65 #[inline(always)]
66 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
67 TX_LSB_FIRST_R::new(((self.bits >> 6) & 1) != 0)
68 }
69 #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit."]
70 #[inline(always)]
71 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
72 RX_LSB_FIRST_R::new(((self.bits >> 7) & 1) != 0)
73 }
74 #[doc = "Bit 8 - Reserved"]
75 #[inline(always)]
76 pub fn clk_en(&self) -> CLK_EN_R {
77 CLK_EN_R::new(((self.bits >> 8) & 1) != 0)
78 }
79 #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
80 #[inline(always)]
81 pub fn arbitration_en(&self) -> ARBITRATION_EN_R {
82 ARBITRATION_EN_R::new(((self.bits >> 9) & 1) != 0)
83 }
84}
85#[cfg(feature = "impl-register-debug")]
86impl core::fmt::Debug for R {
87 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
88 f.debug_struct("CTR")
89 .field("sda_force_out", &self.sda_force_out())
90 .field("scl_force_out", &self.scl_force_out())
91 .field("sample_scl_level", &self.sample_scl_level())
92 .field("rx_full_ack_level", &self.rx_full_ack_level())
93 .field("tx_lsb_first", &self.tx_lsb_first())
94 .field("rx_lsb_first", &self.rx_lsb_first())
95 .field("clk_en", &self.clk_en())
96 .field("arbitration_en", &self.arbitration_en())
97 .finish()
98 }
99}
100impl W {
101 #[doc = "Bit 0 - 1: direct output, 0: open drain output."]
102 #[inline(always)]
103 #[must_use]
104 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTR_SPEC> {
105 SDA_FORCE_OUT_W::new(self, 0)
106 }
107 #[doc = "Bit 1 - 1: direct output, 0: open drain output."]
108 #[inline(always)]
109 #[must_use]
110 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTR_SPEC> {
111 SCL_FORCE_OUT_W::new(self, 1)
112 }
113 #[doc = "Bit 2 - This register is used to select the sample mode. 1: sample SDA data on the SCL low level. 0: sample SDA data on the SCL high level."]
114 #[inline(always)]
115 #[must_use]
116 pub fn sample_scl_level(&mut self) -> SAMPLE_SCL_LEVEL_W<CTR_SPEC> {
117 SAMPLE_SCL_LEVEL_W::new(self, 2)
118 }
119 #[doc = "Bit 3 - This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold."]
120 #[inline(always)]
121 #[must_use]
122 pub fn rx_full_ack_level(&mut self) -> RX_FULL_ACK_LEVEL_W<CTR_SPEC> {
123 RX_FULL_ACK_LEVEL_W::new(self, 3)
124 }
125 #[doc = "Bit 5 - Set this bit to start sending the data in txfifo."]
126 #[inline(always)]
127 #[must_use]
128 pub fn trans_start(&mut self) -> TRANS_START_W<CTR_SPEC> {
129 TRANS_START_W::new(self, 5)
130 }
131 #[doc = "Bit 6 - This bit is used to control the sending mode for data needing to be sent. 1: send data from the least significant bit, 0: send data from the most significant bit."]
132 #[inline(always)]
133 #[must_use]
134 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTR_SPEC> {
135 TX_LSB_FIRST_W::new(self, 6)
136 }
137 #[doc = "Bit 7 - This bit is used to control the storage mode for received data. 1: receive data from the least significant bit, 0: receive data from the most significant bit."]
138 #[inline(always)]
139 #[must_use]
140 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTR_SPEC> {
141 RX_LSB_FIRST_W::new(self, 7)
142 }
143 #[doc = "Bit 8 - Reserved"]
144 #[inline(always)]
145 #[must_use]
146 pub fn clk_en(&mut self) -> CLK_EN_W<CTR_SPEC> {
147 CLK_EN_W::new(self, 8)
148 }
149 #[doc = "Bit 9 - This is the enable bit for arbitration_lost."]
150 #[inline(always)]
151 #[must_use]
152 pub fn arbitration_en(&mut self) -> ARBITRATION_EN_W<CTR_SPEC> {
153 ARBITRATION_EN_W::new(self, 9)
154 }
155 #[doc = "Bit 10 - This register is used to reset the scl FMS."]
156 #[inline(always)]
157 #[must_use]
158 pub fn fsm_rst(&mut self) -> FSM_RST_W<CTR_SPEC> {
159 FSM_RST_W::new(self, 10)
160 }
161 #[doc = "Bit 11 - synchronization bit"]
162 #[inline(always)]
163 #[must_use]
164 pub fn conf_upgate(&mut self) -> CONF_UPGATE_W<CTR_SPEC> {
165 CONF_UPGATE_W::new(self, 11)
166 }
167}
168#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
169pub struct CTR_SPEC;
170impl crate::RegisterSpec for CTR_SPEC {
171 type Ux = u32;
172}
173#[doc = "`read()` method returns [`ctr::R`](R) reader structure"]
174impl crate::Readable for CTR_SPEC {}
175#[doc = "`write(|w| ..)` method takes [`ctr::W`](W) writer structure"]
176impl crate::Writable for CTR_SPEC {
177 type Safety = crate::Unsafe;
178 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
179 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
180}
181#[doc = "`reset()` method sets CTR to value 0x0208"]
182impl crate::Resettable for CTR_SPEC {
183 const RESET_VALUE: u32 = 0x0208;
184}