esp32c6_lp/lp_clkrst/
reset_cause.rs

1#[doc = "Register `RESET_CAUSE` reader"]
2pub type R = crate::R<RESET_CAUSE_SPEC>;
3#[doc = "Register `RESET_CAUSE` writer"]
4pub type W = crate::W<RESET_CAUSE_SPEC>;
5#[doc = "Field `RESET_CAUSE` reader - need_des"]
6pub type RESET_CAUSE_R = crate::FieldReader;
7#[doc = "Field `CORE0_RESET_FLAG` reader - need_des"]
8pub type CORE0_RESET_FLAG_R = crate::BitReader;
9#[doc = "Field `CORE0_RESET_CAUSE_CLR` writer - need_des"]
10pub type CORE0_RESET_CAUSE_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CORE0_RESET_FLAG_SET` writer - need_des"]
12pub type CORE0_RESET_FLAG_SET_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE0_RESET_FLAG_CLR` writer - need_des"]
14pub type CORE0_RESET_FLAG_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15impl R {
16    #[doc = "Bits 0:4 - need_des"]
17    #[inline(always)]
18    pub fn reset_cause(&self) -> RESET_CAUSE_R {
19        RESET_CAUSE_R::new((self.bits & 0x1f) as u8)
20    }
21    #[doc = "Bit 5 - need_des"]
22    #[inline(always)]
23    pub fn core0_reset_flag(&self) -> CORE0_RESET_FLAG_R {
24        CORE0_RESET_FLAG_R::new(((self.bits >> 5) & 1) != 0)
25    }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for R {
29    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
30        f.debug_struct("RESET_CAUSE")
31            .field("reset_cause", &self.reset_cause())
32            .field("core0_reset_flag", &self.core0_reset_flag())
33            .finish()
34    }
35}
36impl W {
37    #[doc = "Bit 29 - need_des"]
38    #[inline(always)]
39    #[must_use]
40    pub fn core0_reset_cause_clr(&mut self) -> CORE0_RESET_CAUSE_CLR_W<RESET_CAUSE_SPEC> {
41        CORE0_RESET_CAUSE_CLR_W::new(self, 29)
42    }
43    #[doc = "Bit 30 - need_des"]
44    #[inline(always)]
45    #[must_use]
46    pub fn core0_reset_flag_set(&mut self) -> CORE0_RESET_FLAG_SET_W<RESET_CAUSE_SPEC> {
47        CORE0_RESET_FLAG_SET_W::new(self, 30)
48    }
49    #[doc = "Bit 31 - need_des"]
50    #[inline(always)]
51    #[must_use]
52    pub fn core0_reset_flag_clr(&mut self) -> CORE0_RESET_FLAG_CLR_W<RESET_CAUSE_SPEC> {
53        CORE0_RESET_FLAG_CLR_W::new(self, 31)
54    }
55}
56#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`reset_cause::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reset_cause::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct RESET_CAUSE_SPEC;
58impl crate::RegisterSpec for RESET_CAUSE_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`reset_cause::R`](R) reader structure"]
62impl crate::Readable for RESET_CAUSE_SPEC {}
63#[doc = "`write(|w| ..)` method takes [`reset_cause::W`](W) writer structure"]
64impl crate::Writable for RESET_CAUSE_SPEC {
65    type Safety = crate::Unsafe;
66    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
67    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
68}
69#[doc = "`reset()` method sets RESET_CAUSE to value 0x20"]
70impl crate::Resettable for RESET_CAUSE_SPEC {
71    const RESET_VALUE: u32 = 0x20;
72}
esp32c6_lp/lp_clkrst/reset_cause.rs

esp32c6_lp/lp_clkrst/
reset_cause.rs
