esp32c6_lp/lp_clkrst/
lp_clk_conf.rs

1#[doc = "Register `LP_CLK_CONF` reader"]
2pub type R = crate::R<LP_CLK_CONF_SPEC>;
3#[doc = "Register `LP_CLK_CONF` writer"]
4pub type W = crate::W<LP_CLK_CONF_SPEC>;
5#[doc = "Field `SLOW_CLK_SEL` reader - need_des"]
6pub type SLOW_CLK_SEL_R = crate::FieldReader;
7#[doc = "Field `SLOW_CLK_SEL` writer - need_des"]
8pub type SLOW_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `FAST_CLK_SEL` reader - need_des"]
10pub type FAST_CLK_SEL_R = crate::BitReader;
11#[doc = "Field `FAST_CLK_SEL` writer - need_des"]
12pub type FAST_CLK_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LP_PERI_DIV_NUM` reader - need_des"]
14pub type LP_PERI_DIV_NUM_R = crate::FieldReader;
15#[doc = "Field `LP_PERI_DIV_NUM` writer - need_des"]
16pub type LP_PERI_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17impl R {
18    #[doc = "Bits 0:1 - need_des"]
19    #[inline(always)]
20    pub fn slow_clk_sel(&self) -> SLOW_CLK_SEL_R {
21        SLOW_CLK_SEL_R::new((self.bits & 3) as u8)
22    }
23    #[doc = "Bit 2 - need_des"]
24    #[inline(always)]
25    pub fn fast_clk_sel(&self) -> FAST_CLK_SEL_R {
26        FAST_CLK_SEL_R::new(((self.bits >> 2) & 1) != 0)
27    }
28    #[doc = "Bits 3:10 - need_des"]
29    #[inline(always)]
30    pub fn lp_peri_div_num(&self) -> LP_PERI_DIV_NUM_R {
31        LP_PERI_DIV_NUM_R::new(((self.bits >> 3) & 0xff) as u8)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("LP_CLK_CONF")
38            .field("slow_clk_sel", &self.slow_clk_sel())
39            .field("fast_clk_sel", &self.fast_clk_sel())
40            .field("lp_peri_div_num", &self.lp_peri_div_num())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:1 - need_des"]
46    #[inline(always)]
47    #[must_use]
48    pub fn slow_clk_sel(&mut self) -> SLOW_CLK_SEL_W<LP_CLK_CONF_SPEC> {
49        SLOW_CLK_SEL_W::new(self, 0)
50    }
51    #[doc = "Bit 2 - need_des"]
52    #[inline(always)]
53    #[must_use]
54    pub fn fast_clk_sel(&mut self) -> FAST_CLK_SEL_W<LP_CLK_CONF_SPEC> {
55        FAST_CLK_SEL_W::new(self, 2)
56    }
57    #[doc = "Bits 3:10 - need_des"]
58    #[inline(always)]
59    #[must_use]
60    pub fn lp_peri_div_num(&mut self) -> LP_PERI_DIV_NUM_W<LP_CLK_CONF_SPEC> {
61        LP_PERI_DIV_NUM_W::new(self, 3)
62    }
63}
64#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`lp_clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lp_clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct LP_CLK_CONF_SPEC;
66impl crate::RegisterSpec for LP_CLK_CONF_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`lp_clk_conf::R`](R) reader structure"]
70impl crate::Readable for LP_CLK_CONF_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`lp_clk_conf::W`](W) writer structure"]
72impl crate::Writable for LP_CLK_CONF_SPEC {
73    type Safety = crate::Unsafe;
74    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
75    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76}
77#[doc = "`reset()` method sets LP_CLK_CONF to value 0x04"]
78impl crate::Resettable for LP_CLK_CONF_SPEC {
79    const RESET_VALUE: u32 = 0x04;
80}
esp32c6_lp/lp_clkrst/lp_clk_conf.rs

esp32c6_lp/lp_clkrst/
lp_clk_conf.rs
