List of all items

Structs

• LP_ANA
• LP_AON
• LP_APM
• LP_CLKRST
• LP_I2C0
• LP_I2C_ANA_MST
• LP_IO
• LP_PERI
• LP_TEE
• LP_TIMER
• LP_UART
• LP_WDT
• PMU
• Peripherals
• generic::Range
• generic::RangeFrom
• generic::RangeTo
• generic::Reg
• generic::Safe
• generic::Unsafe
• lp_ana::RegisterBlock
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNTL_SPEC
• lp_ana::bod_mode1_cntl::BOD_MODE1_CNTL_SPEC
• lp_ana::ck_glitch_cntl::CK_GLITCH_CNTL_SPEC
• lp_ana::date::DATE_SPEC
• lp_ana::fib_enable::FIB_ENABLE_SPEC
• lp_ana::int_clr::INT_CLR_SPEC
• lp_ana::int_ena::INT_ENA_SPEC
• lp_ana::int_raw::INT_RAW_SPEC
• lp_ana::int_st::INT_ST_SPEC
• lp_ana::lp_int_clr::LP_INT_CLR_SPEC
• lp_ana::lp_int_ena::LP_INT_ENA_SPEC
• lp_ana::lp_int_raw::LP_INT_RAW_SPEC
• lp_ana::lp_int_st::LP_INT_ST_SPEC
• lp_aon::RegisterBlock
• lp_aon::cpucore0_cfg::CPUCORE0_CFG_SPEC
• lp_aon::date::DATE_SPEC
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_CNTL_SPEC
• lp_aon::gpio_hold0::GPIO_HOLD0_SPEC
• lp_aon::gpio_hold1::GPIO_HOLD1_SPEC
• lp_aon::gpio_mux::GPIO_MUX_SPEC
• lp_aon::io_mux::IO_MUX_SPEC
• lp_aon::lpbus::LPBUS_SPEC
• lp_aon::lpcore::LPCORE_SPEC
• lp_aon::sar_cct::SAR_CCT_SPEC
• lp_aon::sdio_active::SDIO_ACTIVE_SPEC
• lp_aon::store0::STORE0_SPEC
• lp_aon::store1::STORE1_SPEC
• lp_aon::store2::STORE2_SPEC
• lp_aon::store3::STORE3_SPEC
• lp_aon::store4::STORE4_SPEC
• lp_aon::store5::STORE5_SPEC
• lp_aon::store6::STORE6_SPEC
• lp_aon::store7::STORE7_SPEC
• lp_aon::store8::STORE8_SPEC
• lp_aon::store9::STORE9_SPEC
• lp_aon::sys_cfg::SYS_CFG_SPEC
• lp_aon::usb::USB_SPEC
• lp_apm::RegisterBlock
• lp_apm::clock_gate::CLOCK_GATE_SPEC
• lp_apm::date::DATE_SPEC
• lp_apm::func_ctrl::FUNC_CTRL_SPEC
• lp_apm::int_en::INT_EN_SPEC
• lp_apm::m::M
• lp_apm::m::exception_info0::EXCEPTION_INFO0_SPEC
• lp_apm::m::exception_info1::EXCEPTION_INFO1_SPEC
• lp_apm::m::status::STATUS_SPEC
• lp_apm::m::status_clr::STATUS_CLR_SPEC
• lp_apm::region::REGION
• lp_apm::region::addr_end::ADDR_END_SPEC
• lp_apm::region::addr_start::ADDR_START_SPEC
• lp_apm::region::pms_attr::PMS_ATTR_SPEC
• lp_apm::region_filter_en::REGION_FILTER_EN_SPEC
• lp_clkrst::RegisterBlock
• lp_clkrst::clk_to_hp::CLK_TO_HP_SPEC
• lp_clkrst::cpu_reset::CPU_RESET_SPEC
• lp_clkrst::date::DATE_SPEC
• lp_clkrst::fosc_cntl::FOSC_CNTL_SPEC
• lp_clkrst::lp_clk_conf::LP_CLK_CONF_SPEC
• lp_clkrst::lp_clk_en::LP_CLK_EN_SPEC
• lp_clkrst::lp_clk_po_en::LP_CLK_PO_EN_SPEC
• lp_clkrst::lp_rst_en::LP_RST_EN_SPEC
• lp_clkrst::lpmem_force::LPMEM_FORCE_SPEC
• lp_clkrst::lpperi::LPPERI_SPEC
• lp_clkrst::rc32k_cntl::RC32K_CNTL_SPEC
• lp_clkrst::reset_cause::RESET_CAUSE_SPEC
• lp_clkrst::xtal32k::XTAL32K_SPEC
• lp_i2c0::RegisterBlock
• lp_i2c0::clk_conf::CLK_CONF_SPEC
• lp_i2c0::comd::COMD_SPEC
• lp_i2c0::ctr::CTR_SPEC
• lp_i2c0::data::DATA_SPEC
• lp_i2c0::date::DATE_SPEC
• lp_i2c0::fifo_conf::FIFO_CONF_SPEC
• lp_i2c0::fifo_st::FIFO_ST_SPEC
• lp_i2c0::filter_cfg::FILTER_CFG_SPEC
• lp_i2c0::int_clr::INT_CLR_SPEC
• lp_i2c0::int_ena::INT_ENA_SPEC
• lp_i2c0::int_raw::INT_RAW_SPEC
• lp_i2c0::int_st::INT_ST_SPEC
• lp_i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_SPEC
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_SPEC
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_SPEC
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TIME_OUT_SPEC
• lp_i2c0::scl_rstart_setup::SCL_RSTART_SETUP_SPEC
• lp_i2c0::scl_sp_conf::SCL_SP_CONF_SPEC
• lp_i2c0::scl_st_time_out::SCL_ST_TIME_OUT_SPEC
• lp_i2c0::scl_start_hold::SCL_START_HOLD_SPEC
• lp_i2c0::scl_stop_hold::SCL_STOP_HOLD_SPEC
• lp_i2c0::scl_stop_setup::SCL_STOP_SETUP_SPEC
• lp_i2c0::sda_hold::SDA_HOLD_SPEC
• lp_i2c0::sda_sample::SDA_SAMPLE_SPEC
• lp_i2c0::sr::SR_SPEC
• lp_i2c0::to::TO_SPEC
• lp_i2c0::txfifo_start_addr::TXFIFO_START_ADDR_SPEC
• lp_i2c_ana_mst::RegisterBlock
• lp_i2c_ana_mst::ana_conf1::ANA_CONF1_SPEC
• lp_i2c_ana_mst::date::DATE_SPEC
• lp_i2c_ana_mst::device_en::DEVICE_EN_SPEC
• lp_i2c_ana_mst::i2c0_conf::I2C0_CONF_SPEC
• lp_i2c_ana_mst::i2c0_ctrl::I2C0_CTRL_SPEC
• lp_i2c_ana_mst::i2c0_data::I2C0_DATA_SPEC
• lp_i2c_ana_mst::nouse::NOUSE_SPEC
• lp_io::RegisterBlock
• lp_io::date::DATE_SPEC
• lp_io::enable::ENABLE_SPEC
• lp_io::enable_w1tc::ENABLE_W1TC_SPEC
• lp_io::enable_w1ts::ENABLE_W1TS_SPEC
• lp_io::gpio::GPIO_SPEC
• lp_io::in_::IN_SPEC
• lp_io::out::OUT_SPEC
• lp_io::out_w1tc::OUT_W1TC_SPEC
• lp_io::out_w1ts::OUT_W1TS_SPEC
• lp_io::pin::PIN_SPEC
• lp_io::status::STATUS_SPEC
• lp_io::status_int::STATUS_INT_SPEC
• lp_io::status_w1tc::STATUS_W1TC_SPEC
• lp_io::status_w1ts::STATUS_W1TS_SPEC
• lp_peri::RegisterBlock
• lp_peri::bus_timeout::BUS_TIMEOUT_SPEC
• lp_peri::bus_timeout_addr::BUS_TIMEOUT_ADDR_SPEC
• lp_peri::bus_timeout_uid::BUS_TIMEOUT_UID_SPEC
• lp_peri::clk_en::CLK_EN_SPEC
• lp_peri::cpu::CPU_SPEC
• lp_peri::date::DATE_SPEC
• lp_peri::interrupt_source::INTERRUPT_SOURCE_SPEC
• lp_peri::mem_ctrl::MEM_CTRL_SPEC
• lp_peri::reset_en::RESET_EN_SPEC
• lp_peri::rng_data::RNG_DATA_SPEC
• lp_tee::RegisterBlock
• lp_tee::clock_gate::CLOCK_GATE_SPEC
• lp_tee::date::DATE_SPEC
• lp_tee::force_acc_hp::FORCE_ACC_HP_SPEC
• lp_tee::m_mode_ctrl::M_MODE_CTRL_SPEC
• lp_timer::RegisterBlock
• lp_timer::date::DATE_SPEC
• lp_timer::int_clr::INT_CLR_SPEC
• lp_timer::int_ena::INT_ENA_SPEC
• lp_timer::int_raw::INT_RAW_SPEC
• lp_timer::int_st::INT_ST_SPEC
• lp_timer::lp_int_clr::LP_INT_CLR_SPEC
• lp_timer::lp_int_ena::LP_INT_ENA_SPEC
• lp_timer::lp_int_raw::LP_INT_RAW_SPEC
• lp_timer::lp_int_st::LP_INT_ST_SPEC
• lp_timer::main_buf0_high::MAIN_BUF0_HIGH_SPEC
• lp_timer::main_buf0_low::MAIN_BUF0_LOW_SPEC
• lp_timer::main_buf1_high::MAIN_BUF1_HIGH_SPEC
• lp_timer::main_buf1_low::MAIN_BUF1_LOW_SPEC
• lp_timer::main_overflow::MAIN_OVERFLOW_SPEC
• lp_timer::tar0_high::TAR0_HIGH_SPEC
• lp_timer::tar0_low::TAR0_LOW_SPEC
• lp_timer::tar1_high::TAR1_HIGH_SPEC
• lp_timer::tar1_low::TAR1_LOW_SPEC
• lp_timer::update::UPDATE_SPEC
• lp_uart::RegisterBlock
• lp_uart::afifo_status::AFIFO_STATUS_SPEC
• lp_uart::at_cmd_char_sync::AT_CMD_CHAR_SYNC_SPEC
• lp_uart::at_cmd_gaptout_sync::AT_CMD_GAPTOUT_SYNC_SPEC
• lp_uart::at_cmd_postcnt_sync::AT_CMD_POSTCNT_SYNC_SPEC
• lp_uart::at_cmd_precnt_sync::AT_CMD_PRECNT_SYNC_SPEC
• lp_uart::clk_conf::CLK_CONF_SPEC
• lp_uart::clkdiv_sync::CLKDIV_SYNC_SPEC
• lp_uart::conf0_sync::CONF0_SYNC_SPEC
• lp_uart::conf1::CONF1_SPEC
• lp_uart::date::DATE_SPEC
• lp_uart::fifo::FIFO_SPEC
• lp_uart::fsm_status::FSM_STATUS_SPEC
• lp_uart::hwfc_conf_sync::HWFC_CONF_SYNC_SPEC
• lp_uart::id::ID_SPEC
• lp_uart::idle_conf_sync::IDLE_CONF_SYNC_SPEC
• lp_uart::int_clr::INT_CLR_SPEC
• lp_uart::int_ena::INT_ENA_SPEC
• lp_uart::int_raw::INT_RAW_SPEC
• lp_uart::int_st::INT_ST_SPEC
• lp_uart::mem_conf::MEM_CONF_SPEC
• lp_uart::mem_rx_status::MEM_RX_STATUS_SPEC
• lp_uart::mem_tx_status::MEM_TX_STATUS_SPEC
• lp_uart::reg_update::REG_UPDATE_SPEC
• lp_uart::rs485_conf_sync::RS485_CONF_SYNC_SPEC
• lp_uart::rx_filt::RX_FILT_SPEC
• lp_uart::sleep_conf0::SLEEP_CONF0_SPEC
• lp_uart::sleep_conf1::SLEEP_CONF1_SPEC
• lp_uart::sleep_conf2::SLEEP_CONF2_SPEC
• lp_uart::status::STATUS_SPEC
• lp_uart::swfc_conf0_sync::SWFC_CONF0_SYNC_SPEC
• lp_uart::swfc_conf1::SWFC_CONF1_SPEC
• lp_uart::tout_conf_sync::TOUT_CONF_SYNC_SPEC
• lp_uart::txbrk_conf_sync::TXBRK_CONF_SYNC_SPEC
• lp_wdt::RegisterBlock
• lp_wdt::config0::CONFIG0_SPEC
• lp_wdt::config1::CONFIG1_SPEC
• lp_wdt::config2::CONFIG2_SPEC
• lp_wdt::config3::CONFIG3_SPEC
• lp_wdt::config4::CONFIG4_SPEC
• lp_wdt::date::DATE_SPEC
• lp_wdt::feed::FEED_SPEC
• lp_wdt::int_clr::INT_CLR_SPEC
• lp_wdt::int_ena::INT_ENA_SPEC
• lp_wdt::int_raw::INT_RAW_SPEC
• lp_wdt::int_st::INT_ST_SPEC
• lp_wdt::swd_config::SWD_CONFIG_SPEC
• lp_wdt::swd_wprotect::SWD_WPROTECT_SPEC
• lp_wdt::wprotect::WPROTECT_SPEC
• pmu::RegisterBlock
• pmu::backup_cfg::BACKUP_CFG_SPEC
• pmu::clk_state0::CLK_STATE0_SPEC
• pmu::clk_state1::CLK_STATE1_SPEC
• pmu::clk_state2::CLK_STATE2_SPEC
• pmu::date::DATE_SPEC
• pmu::hp_active_backup::HP_ACTIVE_BACKUP_SPEC
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_CLK_SPEC
• pmu::hp_active_bias::HP_ACTIVE_BIAS_SPEC
• pmu::hp_active_dig_power::HP_ACTIVE_DIG_POWER_SPEC
• pmu::hp_active_hp_ck_power::HP_ACTIVE_HP_CK_POWER_SPEC
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR0_SPEC
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR1_SPEC
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_SYS_CNTL_SPEC
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_ICG_HP_APB_SPEC
• pmu::hp_active_icg_hp_func::HP_ACTIVE_ICG_HP_FUNC_SPEC
• pmu::hp_active_icg_modem::HP_ACTIVE_ICG_MODEM_SPEC
• pmu::hp_active_sysclk::HP_ACTIVE_SYSCLK_SPEC
• pmu::hp_active_xtal::HP_ACTIVE_XTAL_SPEC
• pmu::hp_ck_cntl::HP_CK_CNTL_SPEC
• pmu::hp_ck_poweron::HP_CK_POWERON_SPEC
• pmu::hp_lp_cpu_comm::HP_LP_CPU_COMM_SPEC
• pmu::hp_modem_backup::HP_MODEM_BACKUP_SPEC
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_CLK_SPEC
• pmu::hp_modem_bias::HP_MODEM_BIAS_SPEC
• pmu::hp_modem_dig_power::HP_MODEM_DIG_POWER_SPEC
• pmu::hp_modem_hp_ck_power::HP_MODEM_HP_CK_POWER_SPEC
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR0_SPEC
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR1_SPEC
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_SYS_CNTL_SPEC
• pmu::hp_modem_icg_hp_apb::HP_MODEM_ICG_HP_APB_SPEC
• pmu::hp_modem_icg_hp_func::HP_MODEM_ICG_HP_FUNC_SPEC
• pmu::hp_modem_icg_modem::HP_MODEM_ICG_MODEM_SPEC
• pmu::hp_modem_sysclk::HP_MODEM_SYSCLK_SPEC
• pmu::hp_modem_xtal::HP_MODEM_XTAL_SPEC
• pmu::hp_regulator_cfg::HP_REGULATOR_CFG_SPEC
• pmu::hp_sleep_backup::HP_SLEEP_BACKUP_SPEC
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_CLK_SPEC
• pmu::hp_sleep_bias::HP_SLEEP_BIAS_SPEC
• pmu::hp_sleep_dig_power::HP_SLEEP_DIG_POWER_SPEC
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_HP_CK_POWER_SPEC
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR0_SPEC
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR1_SPEC
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_SYS_CNTL_SPEC
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_ICG_HP_APB_SPEC
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_ICG_HP_FUNC_SPEC
• pmu::hp_sleep_icg_modem::HP_SLEEP_ICG_MODEM_SPEC
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_LP_CK_POWER_SPEC
• pmu::hp_sleep_lp_dcdc_reserve::HP_SLEEP_LP_DCDC_RESERVE_SPEC
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_DIG_POWER_SPEC
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR0_SPEC
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR1_SPEC
• pmu::hp_sleep_sysclk::HP_SLEEP_SYSCLK_SPEC
• pmu::hp_sleep_xtal::HP_SLEEP_XTAL_SPEC
• pmu::imm_hp_apb_icg::IMM_HP_APB_ICG_SPEC
• pmu::imm_hp_ck_power::IMM_HP_CK_POWER_SPEC
• pmu::imm_hp_func_icg::IMM_HP_FUNC_ICG_SPEC
• pmu::imm_i2c_iso::IMM_I2C_ISO_SPEC
• pmu::imm_lp_icg::IMM_LP_ICG_SPEC
• pmu::imm_modem_icg::IMM_MODEM_ICG_SPEC
• pmu::imm_pad_hold_all::IMM_PAD_HOLD_ALL_SPEC
• pmu::imm_sleep_sysclk::IMM_SLEEP_SYSCLK_SPEC
• pmu::int_clr::INT_CLR_SPEC
• pmu::int_ena::INT_ENA_SPEC
• pmu::int_raw::INT_RAW_SPEC
• pmu::int_st::INT_ST_SPEC
• pmu::lp_cpu_pwr0::LP_CPU_PWR0_SPEC
• pmu::lp_cpu_pwr1::LP_CPU_PWR1_SPEC
• pmu::lp_int_clr::LP_INT_CLR_SPEC
• pmu::lp_int_ena::LP_INT_ENA_SPEC
• pmu::lp_int_raw::LP_INT_RAW_SPEC
• pmu::lp_int_st::LP_INT_ST_SPEC
• pmu::lp_sleep_bias::LP_SLEEP_BIAS_SPEC
• pmu::lp_sleep_lp_bias_reserve::LP_SLEEP_LP_BIAS_RESERVE_SPEC
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_LP_CK_POWER_SPEC
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_DIG_POWER_SPEC
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR0_SPEC
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR1_SPEC
• pmu::lp_sleep_xtal::LP_SLEEP_XTAL_SPEC
• pmu::main_state::MAIN_STATE_SPEC
• pmu::por_status::POR_STATUS_SPEC
• pmu::power_ck_wait_cntl::POWER_CK_WAIT_CNTL_SPEC
• pmu::power_hp_pad::POWER_HP_PAD_SPEC
• pmu::power_pd_hpaon_cntl::POWER_PD_HPAON_CNTL_SPEC
• pmu::power_pd_hpcpu_cntl::POWER_PD_HPCPU_CNTL_SPEC
• pmu::power_pd_hpperi_reserve::POWER_PD_HPPERI_RESERVE_SPEC
• pmu::power_pd_hpwifi_cntl::POWER_PD_HPWIFI_CNTL_SPEC
• pmu::power_pd_lpperi_cntl::POWER_PD_LPPERI_CNTL_SPEC
• pmu::power_pd_mem_cntl::POWER_PD_MEM_CNTL_SPEC
• pmu::power_pd_mem_mask::POWER_PD_MEM_MASK_SPEC
• pmu::power_pd_top_cntl::POWER_PD_TOP_CNTL_SPEC
• pmu::power_vdd_spi_cntl::POWER_VDD_SPI_CNTL_SPEC
• pmu::power_wait_timer0::POWER_WAIT_TIMER0_SPEC
• pmu::power_wait_timer1::POWER_WAIT_TIMER1_SPEC
• pmu::pwr_state::PWR_STATE_SPEC
• pmu::rf_pwc::RF_PWC_SPEC
• pmu::slp_wakeup_cntl0::SLP_WAKEUP_CNTL0_SPEC
• pmu::slp_wakeup_cntl1::SLP_WAKEUP_CNTL1_SPEC
• pmu::slp_wakeup_cntl2::SLP_WAKEUP_CNTL2_SPEC
• pmu::slp_wakeup_cntl3::SLP_WAKEUP_CNTL3_SPEC
• pmu::slp_wakeup_cntl4::SLP_WAKEUP_CNTL4_SPEC
• pmu::slp_wakeup_cntl5::SLP_WAKEUP_CNTL5_SPEC
• pmu::slp_wakeup_cntl6::SLP_WAKEUP_CNTL6_SPEC
• pmu::slp_wakeup_cntl7::SLP_WAKEUP_CNTL7_SPEC
• pmu::slp_wakeup_status0::SLP_WAKEUP_STATUS0_SPEC
• pmu::slp_wakeup_status1::SLP_WAKEUP_STATUS1_SPEC
• pmu::vdd_spi_status::VDD_SPI_STATUS_SPEC

Enums

• Interrupt
• lp_tee::m_mode_ctrl::SECURITY_MODE

Traits

• generic::FieldSpec
• generic::IsEnum
• generic::RawReg
• generic::Readable
• generic::RegisterSpec
• generic::Resettable
• generic::Writable

Type Aliases

• generic::BitReader
• generic::BitWriter
• generic::BitWriter0C
• generic::BitWriter0S
• generic::BitWriter0T
• generic::BitWriter1C
• generic::BitWriter1S
• generic::BitWriter1T
• generic::FieldReader
• generic::FieldWriter
• generic::R
• generic::W
• lp_ana::BOD_MODE0_CNTL
• lp_ana::BOD_MODE1_CNTL
• lp_ana::CK_GLITCH_CNTL
• lp_ana::DATE
• lp_ana::FIB_ENABLE
• lp_ana::INT_CLR
• lp_ana::INT_ENA
• lp_ana::INT_RAW
• lp_ana::INT_ST
• lp_ana::LP_INT_CLR
• lp_ana::LP_INT_ENA
• lp_ana::LP_INT_RAW
• lp_ana::LP_INT_ST
• lp_ana::bod_mode0_cntl::BOD_MODE0_CLOSE_FLASH_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_CLOSE_FLASH_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNT_CLR_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNT_CLR_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_WAIT_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_WAIT_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_PD_RF_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_PD_RF_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_SEL_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_SEL_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_WAIT_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_WAIT_W
• lp_ana::bod_mode0_cntl::R
• lp_ana::bod_mode0_cntl::W
• lp_ana::bod_mode1_cntl::BOD_MODE1_RESET_ENA_R
• lp_ana::bod_mode1_cntl::BOD_MODE1_RESET_ENA_W
• lp_ana::bod_mode1_cntl::R
• lp_ana::bod_mode1_cntl::W
• lp_ana::ck_glitch_cntl::CK_GLITCH_RESET_ENA_R
• lp_ana::ck_glitch_cntl::CK_GLITCH_RESET_ENA_W
• lp_ana::ck_glitch_cntl::R
• lp_ana::ck_glitch_cntl::W
• lp_ana::date::CLK_EN_R
• lp_ana::date::CLK_EN_W
• lp_ana::date::LP_ANA_DATE_R
• lp_ana::date::LP_ANA_DATE_W
• lp_ana::date::R
• lp_ana::date::W
• lp_ana::fib_enable::ANA_FIB_ENA_R
• lp_ana::fib_enable::ANA_FIB_ENA_W
• lp_ana::fib_enable::R
• lp_ana::fib_enable::W
• lp_ana::int_clr::BOD_MODE0_W
• lp_ana::int_clr::W
• lp_ana::int_ena::BOD_MODE0_R
• lp_ana::int_ena::BOD_MODE0_W
• lp_ana::int_ena::R
• lp_ana::int_ena::W
• lp_ana::int_raw::BOD_MODE0_R
• lp_ana::int_raw::BOD_MODE0_W
• lp_ana::int_raw::R
• lp_ana::int_raw::W
• lp_ana::int_st::BOD_MODE0_R
• lp_ana::int_st::R
• lp_ana::lp_int_clr::BOD_MODE0_W
• lp_ana::lp_int_clr::W
• lp_ana::lp_int_ena::BOD_MODE0_R
• lp_ana::lp_int_ena::BOD_MODE0_W
• lp_ana::lp_int_ena::R
• lp_ana::lp_int_ena::W
• lp_ana::lp_int_raw::BOD_MODE0_R
• lp_ana::lp_int_raw::BOD_MODE0_W
• lp_ana::lp_int_raw::R
• lp_ana::lp_int_raw::W
• lp_ana::lp_int_st::BOD_MODE0_R
• lp_ana::lp_int_st::R
• lp_aon::CPUCORE0_CFG
• lp_aon::DATE
• lp_aon::EXT_WAKEUP_CNTL
• lp_aon::GPIO_HOLD0
• lp_aon::GPIO_HOLD1
• lp_aon::GPIO_MUX
• lp_aon::IO_MUX
• lp_aon::LPBUS
• lp_aon::LPCORE
• lp_aon::SAR_CCT
• lp_aon::SDIO_ACTIVE
• lp_aon::STORE0
• lp_aon::STORE1
• lp_aon::STORE2
• lp_aon::STORE3
• lp_aon::STORE4
• lp_aon::STORE5
• lp_aon::STORE6
• lp_aon::STORE7
• lp_aon::STORE8
• lp_aon::STORE9
• lp_aon::SYS_CFG
• lp_aon::USB
• lp_aon::cpucore0_cfg::CPU_CORE0_DRESET_MASK_R
• lp_aon::cpucore0_cfg::CPU_CORE0_DRESET_MASK_W
• lp_aon::cpucore0_cfg::CPU_CORE0_OCD_HALT_ON_RESET_R
• lp_aon::cpucore0_cfg::CPU_CORE0_OCD_HALT_ON_RESET_W
• lp_aon::cpucore0_cfg::CPU_CORE0_STAT_VECTOR_SEL_R
• lp_aon::cpucore0_cfg::CPU_CORE0_STAT_VECTOR_SEL_W
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_RESET_W
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_STALL_R
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_STALL_W
• lp_aon::cpucore0_cfg::R
• lp_aon::cpucore0_cfg::W
• lp_aon::date::CLK_EN_R
• lp_aon::date::CLK_EN_W
• lp_aon::date::DATE_R
• lp_aon::date::DATE_W
• lp_aon::date::R
• lp_aon::date::W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_FILTER_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_FILTER_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_LV_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_LV_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_SEL_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_SEL_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_STATUS_CLR_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_STATUS_R
• lp_aon::ext_wakeup_cntl::R
• lp_aon::ext_wakeup_cntl::W
• lp_aon::gpio_hold0::GPIO_HOLD0_R
• lp_aon::gpio_hold0::GPIO_HOLD0_W
• lp_aon::gpio_hold0::R
• lp_aon::gpio_hold0::W
• lp_aon::gpio_hold1::GPIO_HOLD1_R
• lp_aon::gpio_hold1::GPIO_HOLD1_W
• lp_aon::gpio_hold1::R
• lp_aon::gpio_hold1::W
• lp_aon::gpio_mux::R
• lp_aon::gpio_mux::SEL_R
• lp_aon::gpio_mux::SEL_W
• lp_aon::gpio_mux::W
• lp_aon::io_mux::R
• lp_aon::io_mux::RESET_DISABLE_R
• lp_aon::io_mux::RESET_DISABLE_W
• lp_aon::io_mux::W
• lp_aon::lpbus::FAST_MEM_MUX_FSM_IDLE_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_STATUS_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_UPDATE_W
• lp_aon::lpbus::FAST_MEM_MUX_SEL_W
• lp_aon::lpbus::FAST_MEM_RA_R
• lp_aon::lpbus::FAST_MEM_RA_W
• lp_aon::lpbus::FAST_MEM_WA_R
• lp_aon::lpbus::FAST_MEM_WA_W
• lp_aon::lpbus::FAST_MEM_WPULSE_R
• lp_aon::lpbus::FAST_MEM_WPULSE_W
• lp_aon::lpbus::R
• lp_aon::lpbus::W
• lp_aon::lpcore::DISABLE_R
• lp_aon::lpcore::DISABLE_W
• lp_aon::lpcore::ETM_WAKEUP_FLAG_CLR_W
• lp_aon::lpcore::ETM_WAKEUP_FLAG_R
• lp_aon::lpcore::ETM_WAKEUP_FLAG_W
• lp_aon::lpcore::R
• lp_aon::lpcore::W
• lp_aon::sar_cct::R
• lp_aon::sar_cct::SAR2_PWDET_CCT_R
• lp_aon::sar_cct::SAR2_PWDET_CCT_W
• lp_aon::sar_cct::W
• lp_aon::sdio_active::R
• lp_aon::sdio_active::SDIO_ACT_DNUM_R
• lp_aon::sdio_active::SDIO_ACT_DNUM_W
• lp_aon::sdio_active::W
• lp_aon::store0::LP_AON_STORE0_R
• lp_aon::store0::LP_AON_STORE0_W
• lp_aon::store0::R
• lp_aon::store0::W
• lp_aon::store1::LP_AON_STORE1_R
• lp_aon::store1::LP_AON_STORE1_W
• lp_aon::store1::R
• lp_aon::store1::W
• lp_aon::store2::LP_AON_STORE2_R
• lp_aon::store2::LP_AON_STORE2_W
• lp_aon::store2::R
• lp_aon::store2::W
• lp_aon::store3::LP_AON_STORE3_R
• lp_aon::store3::LP_AON_STORE3_W
• lp_aon::store3::R
• lp_aon::store3::W
• lp_aon::store4::LP_AON_STORE4_R
• lp_aon::store4::LP_AON_STORE4_W
• lp_aon::store4::R
• lp_aon::store4::W
• lp_aon::store5::LP_AON_STORE5_R
• lp_aon::store5::LP_AON_STORE5_W
• lp_aon::store5::R
• lp_aon::store5::W
• lp_aon::store6::LP_AON_STORE6_R
• lp_aon::store6::LP_AON_STORE6_W
• lp_aon::store6::R
• lp_aon::store6::W
• lp_aon::store7::LP_AON_STORE7_R
• lp_aon::store7::LP_AON_STORE7_W
• lp_aon::store7::R
• lp_aon::store7::W
• lp_aon::store8::LP_AON_STORE8_R
• lp_aon::store8::LP_AON_STORE8_W
• lp_aon::store8::R
• lp_aon::store8::W
• lp_aon::store9::LP_AON_STORE9_R
• lp_aon::store9::LP_AON_STORE9_W
• lp_aon::store9::R
• lp_aon::store9::W
• lp_aon::sys_cfg::FORCE_DOWNLOAD_BOOT_R
• lp_aon::sys_cfg::FORCE_DOWNLOAD_BOOT_W
• lp_aon::sys_cfg::HPSYS_SW_RESET_W
• lp_aon::sys_cfg::R
• lp_aon::sys_cfg::W
• lp_aon::usb::R
• lp_aon::usb::RESET_DISABLE_R
• lp_aon::usb::RESET_DISABLE_W
• lp_aon::usb::W
• lp_apm::CLOCK_GATE
• lp_apm::DATE
• lp_apm::FUNC_CTRL
• lp_apm::INT_EN
• lp_apm::REGION_FILTER_EN
• lp_apm::clock_gate::CLK_EN_R
• lp_apm::clock_gate::CLK_EN_W
• lp_apm::clock_gate::R
• lp_apm::clock_gate::W
• lp_apm::date::DATE_R
• lp_apm::date::DATE_W
• lp_apm::date::R
• lp_apm::date::W
• lp_apm::func_ctrl::M_PMS_FUNC_EN_R
• lp_apm::func_ctrl::M_PMS_FUNC_EN_W
• lp_apm::func_ctrl::R
• lp_apm::func_ctrl::W
• lp_apm::int_en::M_APM_R
• lp_apm::int_en::M_APM_W
• lp_apm::int_en::R
• lp_apm::int_en::W
• lp_apm::m::EXCEPTION_INFO0
• lp_apm::m::EXCEPTION_INFO1
• lp_apm::m::STATUS
• lp_apm::m::STATUS_CLR
• lp_apm::m::exception_info0::EXCEPTION_ID_R
• lp_apm::m::exception_info0::EXCEPTION_MODE_R
• lp_apm::m::exception_info0::EXCEPTION_REGION_R
• lp_apm::m::exception_info0::R
• lp_apm::m::exception_info1::EXCEPTION_ADDR_R
• lp_apm::m::exception_info1::R
• lp_apm::m::status::EXCEPTION_STATUS_R
• lp_apm::m::status::R
• lp_apm::m::status_clr::REGION_STATUS_CLR_W
• lp_apm::m::status_clr::W
• lp_apm::region::ADDR_END
• lp_apm::region::ADDR_START
• lp_apm::region::PMS_ATTR
• lp_apm::region::addr_end::ADDR_END_R
• lp_apm::region::addr_end::ADDR_END_W
• lp_apm::region::addr_end::R
• lp_apm::region::addr_end::W
• lp_apm::region::addr_start::ADDR_START_R
• lp_apm::region::addr_start::ADDR_START_W
• lp_apm::region::addr_start::R
• lp_apm::region::addr_start::W
• lp_apm::region::pms_attr::R
• lp_apm::region::pms_attr::R_PMS_R_R
• lp_apm::region::pms_attr::R_PMS_R_W
• lp_apm::region::pms_attr::R_PMS_W_R
• lp_apm::region::pms_attr::R_PMS_W_W
• lp_apm::region::pms_attr::R_PMS_X_R
• lp_apm::region::pms_attr::R_PMS_X_W
• lp_apm::region::pms_attr::W
• lp_apm::region_filter_en::R
• lp_apm::region_filter_en::REGION_FILTER_EN_R
• lp_apm::region_filter_en::REGION_FILTER_EN_W
• lp_apm::region_filter_en::W
• lp_clkrst::CLK_TO_HP
• lp_clkrst::CPU_RESET
• lp_clkrst::DATE
• lp_clkrst::FOSC_CNTL
• lp_clkrst::LPMEM_FORCE
• lp_clkrst::LPPERI
• lp_clkrst::LP_CLK_CONF
• lp_clkrst::LP_CLK_EN
• lp_clkrst::LP_CLK_PO_EN
• lp_clkrst::LP_RST_EN
• lp_clkrst::RC32K_CNTL
• lp_clkrst::RESET_CAUSE
• lp_clkrst::XTAL32K
• lp_clkrst::clk_to_hp::ICG_HP_FOSC_R
• lp_clkrst::clk_to_hp::ICG_HP_FOSC_W
• lp_clkrst::clk_to_hp::ICG_HP_OSC32K_R
• lp_clkrst::clk_to_hp::ICG_HP_OSC32K_W
• lp_clkrst::clk_to_hp::ICG_HP_SOSC_R
• lp_clkrst::clk_to_hp::ICG_HP_SOSC_W
• lp_clkrst::clk_to_hp::ICG_HP_XTAL32K_R
• lp_clkrst::clk_to_hp::ICG_HP_XTAL32K_W
• lp_clkrst::clk_to_hp::R
• lp_clkrst::clk_to_hp::W
• lp_clkrst::cpu_reset::CPU_STALL_EN_R
• lp_clkrst::cpu_reset::CPU_STALL_EN_W
• lp_clkrst::cpu_reset::CPU_STALL_WAIT_R
• lp_clkrst::cpu_reset::CPU_STALL_WAIT_W
• lp_clkrst::cpu_reset::R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_EN_R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_EN_W
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_LENGTH_R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_LENGTH_W
• lp_clkrst::cpu_reset::W
• lp_clkrst::date::CLKRST_DATE_R
• lp_clkrst::date::CLKRST_DATE_W
• lp_clkrst::date::CLK_EN_R
• lp_clkrst::date::CLK_EN_W
• lp_clkrst::date::R
• lp_clkrst::date::W
• lp_clkrst::fosc_cntl::FOSC_DFREQ_R
• lp_clkrst::fosc_cntl::FOSC_DFREQ_W
• lp_clkrst::fosc_cntl::R
• lp_clkrst::fosc_cntl::W
• lp_clkrst::lp_clk_conf::FAST_CLK_SEL_R
• lp_clkrst::lp_clk_conf::FAST_CLK_SEL_W
• lp_clkrst::lp_clk_conf::LP_PERI_DIV_NUM_R
• lp_clkrst::lp_clk_conf::LP_PERI_DIV_NUM_W
• lp_clkrst::lp_clk_conf::R
• lp_clkrst::lp_clk_conf::SLOW_CLK_SEL_R
• lp_clkrst::lp_clk_conf::SLOW_CLK_SEL_W
• lp_clkrst::lp_clk_conf::W
• lp_clkrst::lp_clk_en::FAST_ORI_GATE_R
• lp_clkrst::lp_clk_en::FAST_ORI_GATE_W
• lp_clkrst::lp_clk_en::R
• lp_clkrst::lp_clk_en::W
• lp_clkrst::lp_clk_po_en::AON_FAST_OEN_R
• lp_clkrst::lp_clk_po_en::AON_FAST_OEN_W
• lp_clkrst::lp_clk_po_en::AON_SLOW_OEN_R
• lp_clkrst::lp_clk_po_en::AON_SLOW_OEN_W
• lp_clkrst::lp_clk_po_en::CORE_EFUSE_OEN_R
• lp_clkrst::lp_clk_po_en::CORE_EFUSE_OEN_W
• lp_clkrst::lp_clk_po_en::FAST_OEN_R
• lp_clkrst::lp_clk_po_en::FAST_OEN_W
• lp_clkrst::lp_clk_po_en::FOSC_OEN_R
• lp_clkrst::lp_clk_po_en::FOSC_OEN_W
• lp_clkrst::lp_clk_po_en::LPBUS_OEN_R
• lp_clkrst::lp_clk_po_en::LPBUS_OEN_W
• lp_clkrst::lp_clk_po_en::OSC32K_OEN_R
• lp_clkrst::lp_clk_po_en::OSC32K_OEN_W
• lp_clkrst::lp_clk_po_en::R
• lp_clkrst::lp_clk_po_en::RNG_OEN_R
• lp_clkrst::lp_clk_po_en::RNG_OEN_W
• lp_clkrst::lp_clk_po_en::SLOW_OEN_R
• lp_clkrst::lp_clk_po_en::SLOW_OEN_W
• lp_clkrst::lp_clk_po_en::SOSC_OEN_R
• lp_clkrst::lp_clk_po_en::SOSC_OEN_W
• lp_clkrst::lp_clk_po_en::W
• lp_clkrst::lp_clk_po_en::XTAL32K_OEN_R
• lp_clkrst::lp_clk_po_en::XTAL32K_OEN_W
• lp_clkrst::lp_rst_en::ANA_PERI_RESET_EN_R
• lp_clkrst::lp_rst_en::ANA_PERI_RESET_EN_W
• lp_clkrst::lp_rst_en::AON_EFUSE_CORE_RESET_EN_R
• lp_clkrst::lp_rst_en::AON_EFUSE_CORE_RESET_EN_W
• lp_clkrst::lp_rst_en::LP_TIMER_RESET_EN_R
• lp_clkrst::lp_rst_en::LP_TIMER_RESET_EN_W
• lp_clkrst::lp_rst_en::R
• lp_clkrst::lp_rst_en::W
• lp_clkrst::lp_rst_en::WDT_RESET_EN_R
• lp_clkrst::lp_rst_en::WDT_RESET_EN_W
• lp_clkrst::lpmem_force::LPMEM_CLK_FORCE_ON_R
• lp_clkrst::lpmem_force::LPMEM_CLK_FORCE_ON_W
• lp_clkrst::lpmem_force::R
• lp_clkrst::lpmem_force::W
• lp_clkrst::lpperi::LP_I2C_CLK_SEL_R
• lp_clkrst::lpperi::LP_I2C_CLK_SEL_W
• lp_clkrst::lpperi::LP_UART_CLK_SEL_R
• lp_clkrst::lpperi::LP_UART_CLK_SEL_W
• lp_clkrst::lpperi::R
• lp_clkrst::lpperi::W
• lp_clkrst::rc32k_cntl::R
• lp_clkrst::rc32k_cntl::RC32K_DFREQ_R
• lp_clkrst::rc32k_cntl::RC32K_DFREQ_W
• lp_clkrst::rc32k_cntl::W
• lp_clkrst::reset_cause::CORE0_RESET_CAUSE_CLR_W
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_CLR_W
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_R
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_SET_W
• lp_clkrst::reset_cause::R
• lp_clkrst::reset_cause::RESET_CAUSE_R
• lp_clkrst::reset_cause::W
• lp_clkrst::xtal32k::DAC_XTAL32K_R
• lp_clkrst::xtal32k::DAC_XTAL32K_W
• lp_clkrst::xtal32k::DBUF_XTAL32K_R
• lp_clkrst::xtal32k::DBUF_XTAL32K_W
• lp_clkrst::xtal32k::DGM_XTAL32K_R
• lp_clkrst::xtal32k::DGM_XTAL32K_W
• lp_clkrst::xtal32k::DRES_XTAL32K_R
• lp_clkrst::xtal32k::DRES_XTAL32K_W
• lp_clkrst::xtal32k::R
• lp_clkrst::xtal32k::W
• lp_i2c0::CLK_CONF
• lp_i2c0::COMD
• lp_i2c0::CTR
• lp_i2c0::DATA
• lp_i2c0::DATE
• lp_i2c0::FIFO_CONF
• lp_i2c0::FIFO_ST
• lp_i2c0::FILTER_CFG
• lp_i2c0::INT_CLR
• lp_i2c0::INT_ENA
• lp_i2c0::INT_RAW
• lp_i2c0::INT_ST
• lp_i2c0::RXFIFO_START_ADDR
• lp_i2c0::SCL_HIGH_PERIOD
• lp_i2c0::SCL_LOW_PERIOD
• lp_i2c0::SCL_MAIN_ST_TIME_OUT
• lp_i2c0::SCL_RSTART_SETUP
• lp_i2c0::SCL_SP_CONF
• lp_i2c0::SCL_START_HOLD
• lp_i2c0::SCL_STOP_HOLD
• lp_i2c0::SCL_STOP_SETUP
• lp_i2c0::SCL_ST_TIME_OUT
• lp_i2c0::SDA_HOLD
• lp_i2c0::SDA_SAMPLE
• lp_i2c0::SR
• lp_i2c0::TO
• lp_i2c0::TXFIFO_START_ADDR
• lp_i2c0::clk_conf::R
• lp_i2c0::clk_conf::SCLK_ACTIVE_R
• lp_i2c0::clk_conf::SCLK_ACTIVE_W
• lp_i2c0::clk_conf::SCLK_DIV_A_R
• lp_i2c0::clk_conf::SCLK_DIV_A_W
• lp_i2c0::clk_conf::SCLK_DIV_B_R
• lp_i2c0::clk_conf::SCLK_DIV_B_W
• lp_i2c0::clk_conf::SCLK_DIV_NUM_R
• lp_i2c0::clk_conf::SCLK_DIV_NUM_W
• lp_i2c0::clk_conf::SCLK_SEL_R
• lp_i2c0::clk_conf::SCLK_SEL_W
• lp_i2c0::clk_conf::W
• lp_i2c0::comd::COMMAND_DONE_R
• lp_i2c0::comd::COMMAND_DONE_W
• lp_i2c0::comd::COMMAND_R
• lp_i2c0::comd::COMMAND_W
• lp_i2c0::comd::R
• lp_i2c0::comd::W
• lp_i2c0::ctr::ARBITRATION_EN_R
• lp_i2c0::ctr::ARBITRATION_EN_W
• lp_i2c0::ctr::CLK_EN_R
• lp_i2c0::ctr::CLK_EN_W
• lp_i2c0::ctr::CONF_UPGATE_W
• lp_i2c0::ctr::FSM_RST_W
• lp_i2c0::ctr::R
• lp_i2c0::ctr::RX_FULL_ACK_LEVEL_R
• lp_i2c0::ctr::RX_FULL_ACK_LEVEL_W
• lp_i2c0::ctr::RX_LSB_FIRST_R
• lp_i2c0::ctr::RX_LSB_FIRST_W
• lp_i2c0::ctr::SAMPLE_SCL_LEVEL_R
• lp_i2c0::ctr::SAMPLE_SCL_LEVEL_W
• lp_i2c0::ctr::SCL_FORCE_OUT_R
• lp_i2c0::ctr::SCL_FORCE_OUT_W
• lp_i2c0::ctr::SDA_FORCE_OUT_R
• lp_i2c0::ctr::SDA_FORCE_OUT_W
• lp_i2c0::ctr::TRANS_START_W
• lp_i2c0::ctr::TX_LSB_FIRST_R
• lp_i2c0::ctr::TX_LSB_FIRST_W
• lp_i2c0::ctr::W
• lp_i2c0::data::FIFO_RDATA_R
• lp_i2c0::data::FIFO_RDATA_W
• lp_i2c0::data::R
• lp_i2c0::data::W
• lp_i2c0::date::DATE_R
• lp_i2c0::date::DATE_W
• lp_i2c0::date::R
• lp_i2c0::date::W
• lp_i2c0::fifo_conf::FIFO_PRT_EN_R
• lp_i2c0::fifo_conf::FIFO_PRT_EN_W
• lp_i2c0::fifo_conf::NONFIFO_EN_R
• lp_i2c0::fifo_conf::NONFIFO_EN_W
• lp_i2c0::fifo_conf::R
• lp_i2c0::fifo_conf::RXFIFO_WM_THRHD_R
• lp_i2c0::fifo_conf::RXFIFO_WM_THRHD_W
• lp_i2c0::fifo_conf::RX_FIFO_RST_R
• lp_i2c0::fifo_conf::RX_FIFO_RST_W
• lp_i2c0::fifo_conf::TXFIFO_WM_THRHD_R
• lp_i2c0::fifo_conf::TXFIFO_WM_THRHD_W
• lp_i2c0::fifo_conf::TX_FIFO_RST_R
• lp_i2c0::fifo_conf::TX_FIFO_RST_W
• lp_i2c0::fifo_conf::W
• lp_i2c0::fifo_st::R
• lp_i2c0::fifo_st::RXFIFO_RADDR_R
• lp_i2c0::fifo_st::RXFIFO_WADDR_R
• lp_i2c0::fifo_st::TXFIFO_RADDR_R
• lp_i2c0::fifo_st::TXFIFO_WADDR_R
• lp_i2c0::filter_cfg::R
• lp_i2c0::filter_cfg::SCL_FILTER_EN_R
• lp_i2c0::filter_cfg::SCL_FILTER_EN_W
• lp_i2c0::filter_cfg::SCL_FILTER_THRES_R
• lp_i2c0::filter_cfg::SCL_FILTER_THRES_W
• lp_i2c0::filter_cfg::SDA_FILTER_EN_R
• lp_i2c0::filter_cfg::SDA_FILTER_EN_W
• lp_i2c0::filter_cfg::SDA_FILTER_THRES_R
• lp_i2c0::filter_cfg::SDA_FILTER_THRES_W
• lp_i2c0::filter_cfg::W
• lp_i2c0::int_clr::ARBITRATION_LOST_W
• lp_i2c0::int_clr::BYTE_TRANS_DONE_W
• lp_i2c0::int_clr::DET_START_W
• lp_i2c0::int_clr::END_DETECT_W
• lp_i2c0::int_clr::MST_TXFIFO_UDF_W
• lp_i2c0::int_clr::NACK_W
• lp_i2c0::int_clr::RXFIFO_OVF_W
• lp_i2c0::int_clr::RXFIFO_UDF_W
• lp_i2c0::int_clr::RXFIFO_WM_W
• lp_i2c0::int_clr::SCL_MAIN_ST_TO_W
• lp_i2c0::int_clr::SCL_ST_TO_W
• lp_i2c0::int_clr::TIME_OUT_W
• lp_i2c0::int_clr::TRANS_COMPLETE_W
• lp_i2c0::int_clr::TRANS_START_W
• lp_i2c0::int_clr::TXFIFO_OVF_W
• lp_i2c0::int_clr::TXFIFO_WM_W
• lp_i2c0::int_clr::W
• lp_i2c0::int_ena::ARBITRATION_LOST_R
• lp_i2c0::int_ena::ARBITRATION_LOST_W
• lp_i2c0::int_ena::BYTE_TRANS_DONE_R
• lp_i2c0::int_ena::BYTE_TRANS_DONE_W
• lp_i2c0::int_ena::DET_START_R
• lp_i2c0::int_ena::DET_START_W
• lp_i2c0::int_ena::END_DETECT_R
• lp_i2c0::int_ena::END_DETECT_W
• lp_i2c0::int_ena::MST_TXFIFO_UDF_R
• lp_i2c0::int_ena::MST_TXFIFO_UDF_W
• lp_i2c0::int_ena::NACK_R
• lp_i2c0::int_ena::NACK_W
• lp_i2c0::int_ena::R
• lp_i2c0::int_ena::RXFIFO_OVF_R
• lp_i2c0::int_ena::RXFIFO_OVF_W
• lp_i2c0::int_ena::RXFIFO_UDF_R
• lp_i2c0::int_ena::RXFIFO_UDF_W
• lp_i2c0::int_ena::RXFIFO_WM_R
• lp_i2c0::int_ena::RXFIFO_WM_W
• lp_i2c0::int_ena::SCL_MAIN_ST_TO_R
• lp_i2c0::int_ena::SCL_MAIN_ST_TO_W
• lp_i2c0::int_ena::SCL_ST_TO_R
• lp_i2c0::int_ena::SCL_ST_TO_W
• lp_i2c0::int_ena::TIME_OUT_R
• lp_i2c0::int_ena::TIME_OUT_W
• lp_i2c0::int_ena::TRANS_COMPLETE_R
• lp_i2c0::int_ena::TRANS_COMPLETE_W
• lp_i2c0::int_ena::TRANS_START_R
• lp_i2c0::int_ena::TRANS_START_W
• lp_i2c0::int_ena::TXFIFO_OVF_R
• lp_i2c0::int_ena::TXFIFO_OVF_W
• lp_i2c0::int_ena::TXFIFO_WM_R
• lp_i2c0::int_ena::TXFIFO_WM_W
• lp_i2c0::int_ena::W
• lp_i2c0::int_raw::ARBITRATION_LOST_R
• lp_i2c0::int_raw::BYTE_TRANS_DONE_R
• lp_i2c0::int_raw::DET_START_R
• lp_i2c0::int_raw::END_DETECT_R
• lp_i2c0::int_raw::MST_TXFIFO_UDF_R
• lp_i2c0::int_raw::NACK_R
• lp_i2c0::int_raw::R
• lp_i2c0::int_raw::RXFIFO_OVF_R
• lp_i2c0::int_raw::RXFIFO_UDF_R
• lp_i2c0::int_raw::RXFIFO_WM_R
• lp_i2c0::int_raw::SCL_MAIN_ST_TO_R
• lp_i2c0::int_raw::SCL_ST_TO_R
• lp_i2c0::int_raw::TIME_OUT_R
• lp_i2c0::int_raw::TRANS_COMPLETE_R
• lp_i2c0::int_raw::TRANS_START_R
• lp_i2c0::int_raw::TXFIFO_OVF_R
• lp_i2c0::int_raw::TXFIFO_WM_R
• lp_i2c0::int_st::ARBITRATION_LOST_R
• lp_i2c0::int_st::BYTE_TRANS_DONE_R
• lp_i2c0::int_st::DET_START_R
• lp_i2c0::int_st::END_DETECT_R
• lp_i2c0::int_st::MST_TXFIFO_UDF_R
• lp_i2c0::int_st::NACK_R
• lp_i2c0::int_st::R
• lp_i2c0::int_st::RXFIFO_OVF_R
• lp_i2c0::int_st::RXFIFO_UDF_R
• lp_i2c0::int_st::RXFIFO_WM_R
• lp_i2c0::int_st::SCL_MAIN_ST_TO_R
• lp_i2c0::int_st::SCL_ST_TO_R
• lp_i2c0::int_st::TIME_OUT_R
• lp_i2c0::int_st::TRANS_COMPLETE_R
• lp_i2c0::int_st::TRANS_START_R
• lp_i2c0::int_st::TXFIFO_OVF_R
• lp_i2c0::int_st::TXFIFO_WM_R
• lp_i2c0::rxfifo_start_addr::R
• lp_i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_R
• lp_i2c0::scl_high_period::R
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_R
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_W
• lp_i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_R
• lp_i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_W
• lp_i2c0::scl_high_period::W
• lp_i2c0::scl_low_period::R
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_R
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_W
• lp_i2c0::scl_low_period::W
• lp_i2c0::scl_main_st_time_out::R
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_I2C_R
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_I2C_W
• lp_i2c0::scl_main_st_time_out::W
• lp_i2c0::scl_rstart_setup::R
• lp_i2c0::scl_rstart_setup::TIME_R
• lp_i2c0::scl_rstart_setup::TIME_W
• lp_i2c0::scl_rstart_setup::W
• lp_i2c0::scl_sp_conf::R
• lp_i2c0::scl_sp_conf::SCL_PD_EN_R
• lp_i2c0::scl_sp_conf::SCL_PD_EN_W
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_EN_R
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_EN_W
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_NUM_R
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_NUM_W
• lp_i2c0::scl_sp_conf::SDA_PD_EN_R
• lp_i2c0::scl_sp_conf::SDA_PD_EN_W
• lp_i2c0::scl_sp_conf::W
• lp_i2c0::scl_st_time_out::R
• lp_i2c0::scl_st_time_out::SCL_ST_TO_I2C_R
• lp_i2c0::scl_st_time_out::SCL_ST_TO_I2C_W
• lp_i2c0::scl_st_time_out::W
• lp_i2c0::scl_start_hold::R
• lp_i2c0::scl_start_hold::TIME_R
• lp_i2c0::scl_start_hold::TIME_W
• lp_i2c0::scl_start_hold::W
• lp_i2c0::scl_stop_hold::R
• lp_i2c0::scl_stop_hold::TIME_R
• lp_i2c0::scl_stop_hold::TIME_W
• lp_i2c0::scl_stop_hold::W
• lp_i2c0::scl_stop_setup::R
• lp_i2c0::scl_stop_setup::TIME_R
• lp_i2c0::scl_stop_setup::TIME_W
• lp_i2c0::scl_stop_setup::W
• lp_i2c0::sda_hold::R
• lp_i2c0::sda_hold::TIME_R
• lp_i2c0::sda_hold::TIME_W
• lp_i2c0::sda_hold::W
• lp_i2c0::sda_sample::R
• lp_i2c0::sda_sample::TIME_R
• lp_i2c0::sda_sample::TIME_W
• lp_i2c0::sda_sample::W
• lp_i2c0::sr::ARB_LOST_R
• lp_i2c0::sr::BUS_BUSY_R
• lp_i2c0::sr::R
• lp_i2c0::sr::RESP_REC_R
• lp_i2c0::sr::RXFIFO_CNT_R
• lp_i2c0::sr::SCL_MAIN_STATE_LAST_R
• lp_i2c0::sr::SCL_STATE_LAST_R
• lp_i2c0::sr::TXFIFO_CNT_R
• lp_i2c0::to::R
• lp_i2c0::to::TIME_OUT_EN_R
• lp_i2c0::to::TIME_OUT_EN_W
• lp_i2c0::to::TIME_OUT_VALUE_R
• lp_i2c0::to::TIME_OUT_VALUE_W
• lp_i2c0::to::W
• lp_i2c0::txfifo_start_addr::R
• lp_i2c0::txfifo_start_addr::TXFIFO_START_ADDR_R
• lp_i2c_ana_mst::ANA_CONF1
• lp_i2c_ana_mst::DATE
• lp_i2c_ana_mst::DEVICE_EN
• lp_i2c_ana_mst::I2C0_CONF
• lp_i2c_ana_mst::I2C0_CTRL
• lp_i2c_ana_mst::I2C0_DATA
• lp_i2c_ana_mst::NOUSE
• lp_i2c_ana_mst::ana_conf1::LP_I2C_ANA_MAST_ANA_CONF1_R
• lp_i2c_ana_mst::ana_conf1::LP_I2C_ANA_MAST_ANA_CONF1_W
• lp_i2c_ana_mst::ana_conf1::R
• lp_i2c_ana_mst::ana_conf1::W
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_R
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_W
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_DATE_R
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_DATE_W
• lp_i2c_ana_mst::date::R
• lp_i2c_ana_mst::date::W
• lp_i2c_ana_mst::device_en::LP_I2C_ANA_MAST_I2C_DEVICE_EN_R
• lp_i2c_ana_mst::device_en::LP_I2C_ANA_MAST_I2C_DEVICE_EN_W
• lp_i2c_ana_mst::device_en::R
• lp_i2c_ana_mst::device_en::W
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_CONF_R
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_CONF_W
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_STATUS_R
• lp_i2c_ana_mst::i2c0_conf::R
• lp_i2c_ana_mst::i2c0_conf::W
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_BUSY_R
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_CTRL_R
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_CTRL_W
• lp_i2c_ana_mst::i2c0_ctrl::R
• lp_i2c_ana_mst::i2c0_ctrl::W
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_CLK_SEL_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_CLK_SEL_W
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_RDATA_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C_MST_SEL_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C_MST_SEL_W
• lp_i2c_ana_mst::i2c0_data::R
• lp_i2c_ana_mst::i2c0_data::W
• lp_i2c_ana_mst::nouse::LP_I2C_ANA_MAST_I2C_MST_NOUSE_R
• lp_i2c_ana_mst::nouse::LP_I2C_ANA_MAST_I2C_MST_NOUSE_W
• lp_i2c_ana_mst::nouse::R
• lp_i2c_ana_mst::nouse::W
• lp_io::DATE
• lp_io::ENABLE
• lp_io::ENABLE_W1TC
• lp_io::ENABLE_W1TS
• lp_io::GPIO
• lp_io::IN
• lp_io::OUT
• lp_io::OUT_W1TC
• lp_io::OUT_W1TS
• lp_io::PIN
• lp_io::STATUS
• lp_io::STATUS_INT
• lp_io::STATUS_W1TC
• lp_io::STATUS_W1TS
• lp_io::date::CLK_EN_R
• lp_io::date::CLK_EN_W
• lp_io::date::LP_IO_DATE_R
• lp_io::date::LP_IO_DATE_W
• lp_io::date::R
• lp_io::date::W
• lp_io::enable::ENABLE_R
• lp_io::enable::ENABLE_W
• lp_io::enable::R
• lp_io::enable::W
• lp_io::enable_w1tc::ENABLE_W1TC_W
• lp_io::enable_w1tc::W
• lp_io::enable_w1ts::ENABLE_W1TS_W
• lp_io::enable_w1ts::W
• lp_io::gpio::FUN_DRV_R
• lp_io::gpio::FUN_DRV_W
• lp_io::gpio::FUN_IE_R
• lp_io::gpio::FUN_IE_W
• lp_io::gpio::FUN_SEL_R
• lp_io::gpio::FUN_SEL_W
• lp_io::gpio::FUN_WPD_R
• lp_io::gpio::FUN_WPD_W
• lp_io::gpio::FUN_WPU_R
• lp_io::gpio::FUN_WPU_W
• lp_io::gpio::MCU_DRV_R
• lp_io::gpio::MCU_DRV_W
• lp_io::gpio::MCU_IE_R
• lp_io::gpio::MCU_IE_W
• lp_io::gpio::MCU_OE_R
• lp_io::gpio::MCU_OE_W
• lp_io::gpio::MCU_WPD_R
• lp_io::gpio::MCU_WPD_W
• lp_io::gpio::MCU_WPU_R
• lp_io::gpio::MCU_WPU_W
• lp_io::gpio::R
• lp_io::gpio::SLP_SEL_R
• lp_io::gpio::SLP_SEL_W
• lp_io::gpio::W
• lp_io::in_::DATA_NEXT_R
• lp_io::in_::R
• lp_io::out::OUT_DATA_R
• lp_io::out::OUT_DATA_W
• lp_io::out::R
• lp_io::out::W
• lp_io::out_w1tc::OUT_DATA_W1TC_W
• lp_io::out_w1tc::W
• lp_io::out_w1ts::OUT_DATA_W1TS_W
• lp_io::out_w1ts::W
• lp_io::pin::EDGE_WAKEUP_CLR_W
• lp_io::pin::FILTER_EN_R
• lp_io::pin::FILTER_EN_W
• lp_io::pin::INT_TYPE_R
• lp_io::pin::INT_TYPE_W
• lp_io::pin::PAD_DRIVER_R
• lp_io::pin::PAD_DRIVER_W
• lp_io::pin::R
• lp_io::pin::SYNC_BYPASS_R
• lp_io::pin::SYNC_BYPASS_W
• lp_io::pin::W
• lp_io::pin::WAKEUP_ENABLE_R
• lp_io::pin::WAKEUP_ENABLE_W
• lp_io::status::INTERRUPT_R
• lp_io::status::INTERRUPT_W
• lp_io::status::R
• lp_io::status::W
• lp_io::status_int::NEXT_R
• lp_io::status_int::R
• lp_io::status_w1tc::STATUS_W1TC_W
• lp_io::status_w1tc::W
• lp_io::status_w1ts::STATUS_W1TS_W
• lp_io::status_w1ts::W
• lp_peri::BUS_TIMEOUT
• lp_peri::BUS_TIMEOUT_ADDR
• lp_peri::BUS_TIMEOUT_UID
• lp_peri::CLK_EN
• lp_peri::CPU
• lp_peri::DATE
• lp_peri::INTERRUPT_SOURCE
• lp_peri::MEM_CTRL
• lp_peri::RESET_EN
• lp_peri::RNG_DATA
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_INT_CLEAR_W
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_PROTECT_EN_R
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_PROTECT_EN_W
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_THRES_R
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_THRES_W
• lp_peri::bus_timeout::R
• lp_peri::bus_timeout::W
• lp_peri::bus_timeout_addr::LP_PERI_TIMEOUT_ADDR_R
• lp_peri::bus_timeout_addr::R
• lp_peri::bus_timeout_uid::LP_PERI_TIMEOUT_UID_R
• lp_peri::bus_timeout_uid::R
• lp_peri::clk_en::EFUSE_CK_EN_R
• lp_peri::clk_en::EFUSE_CK_EN_W
• lp_peri::clk_en::LP_ANA_I2C_CK_EN_R
• lp_peri::clk_en::LP_ANA_I2C_CK_EN_W
• lp_peri::clk_en::LP_CPU_CK_EN_R
• lp_peri::clk_en::LP_CPU_CK_EN_W
• lp_peri::clk_en::LP_EXT_I2C_CK_EN_R
• lp_peri::clk_en::LP_EXT_I2C_CK_EN_W
• lp_peri::clk_en::LP_IO_CK_EN_R
• lp_peri::clk_en::LP_IO_CK_EN_W
• lp_peri::clk_en::LP_TOUCH_CK_EN_R
• lp_peri::clk_en::LP_TOUCH_CK_EN_W
• lp_peri::clk_en::LP_UART_CK_EN_R
• lp_peri::clk_en::LP_UART_CK_EN_W
• lp_peri::clk_en::OTP_DBG_CK_EN_R
• lp_peri::clk_en::OTP_DBG_CK_EN_W
• lp_peri::clk_en::R
• lp_peri::clk_en::RNG_CK_EN_R
• lp_peri::clk_en::RNG_CK_EN_W
• lp_peri::clk_en::W
• lp_peri::cpu::LPCORE_DBGM_UNAVALIABLE_R
• lp_peri::cpu::LPCORE_DBGM_UNAVALIABLE_W
• lp_peri::cpu::R
• lp_peri::cpu::W
• lp_peri::date::CLK_EN_R
• lp_peri::date::CLK_EN_W
• lp_peri::date::LPPERI_DATE_R
• lp_peri::date::LPPERI_DATE_W
• lp_peri::date::R
• lp_peri::date::W
• lp_peri::interrupt_source::LP_INTERRUPT_SOURCE_R
• lp_peri::interrupt_source::R
• lp_peri::mem_ctrl::R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PD_R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PD_W
• lp_peri::mem_ctrl::UART_MEM_FORCE_PU_R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PU_W
• lp_peri::mem_ctrl::UART_WAKEUP_EN_R
• lp_peri::mem_ctrl::UART_WAKEUP_EN_W
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_CLR_W
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_R
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_W
• lp_peri::mem_ctrl::W
• lp_peri::reset_en::BUS_RESET_EN_W
• lp_peri::reset_en::EFUSE_RESET_EN_R
• lp_peri::reset_en::EFUSE_RESET_EN_W
• lp_peri::reset_en::LP_ANA_I2C_RESET_EN_R
• lp_peri::reset_en::LP_ANA_I2C_RESET_EN_W
• lp_peri::reset_en::LP_CPU_RESET_EN_W
• lp_peri::reset_en::LP_EXT_I2C_RESET_EN_R
• lp_peri::reset_en::LP_EXT_I2C_RESET_EN_W
• lp_peri::reset_en::LP_IO_RESET_EN_R
• lp_peri::reset_en::LP_IO_RESET_EN_W
• lp_peri::reset_en::LP_TOUCH_RESET_EN_R
• lp_peri::reset_en::LP_TOUCH_RESET_EN_W
• lp_peri::reset_en::LP_UART_RESET_EN_R
• lp_peri::reset_en::LP_UART_RESET_EN_W
• lp_peri::reset_en::OTP_DBG_RESET_EN_R
• lp_peri::reset_en::OTP_DBG_RESET_EN_W
• lp_peri::reset_en::R
• lp_peri::reset_en::W
• lp_peri::rng_data::R
• lp_peri::rng_data::RND_DATA_R
• lp_tee::CLOCK_GATE
• lp_tee::DATE
• lp_tee::FORCE_ACC_HP
• lp_tee::M_MODE_CTRL
• lp_tee::clock_gate::CLK_EN_R
• lp_tee::clock_gate::CLK_EN_W
• lp_tee::clock_gate::R
• lp_tee::clock_gate::W
• lp_tee::date::DATE_R
• lp_tee::date::DATE_W
• lp_tee::date::R
• lp_tee::date::W
• lp_tee::force_acc_hp::LP_AON_FORCE_ACC_HPMEM_EN_R
• lp_tee::force_acc_hp::LP_AON_FORCE_ACC_HPMEM_EN_W
• lp_tee::force_acc_hp::R
• lp_tee::force_acc_hp::W
• lp_tee::m_mode_ctrl::MODE_R
• lp_tee::m_mode_ctrl::MODE_W
• lp_tee::m_mode_ctrl::R
• lp_tee::m_mode_ctrl::W
• lp_timer::DATE
• lp_timer::INT_CLR
• lp_timer::INT_ENA
• lp_timer::INT_RAW
• lp_timer::INT_ST
• lp_timer::LP_INT_CLR
• lp_timer::LP_INT_ENA
• lp_timer::LP_INT_RAW
• lp_timer::LP_INT_ST
• lp_timer::MAIN_BUF0_HIGH
• lp_timer::MAIN_BUF0_LOW
• lp_timer::MAIN_BUF1_HIGH
• lp_timer::MAIN_BUF1_LOW
• lp_timer::MAIN_OVERFLOW
• lp_timer::TAR0_HIGH
• lp_timer::TAR0_LOW
• lp_timer::TAR1_HIGH
• lp_timer::TAR1_LOW
• lp_timer::UPDATE
• lp_timer::date::CLK_EN_R
• lp_timer::date::CLK_EN_W
• lp_timer::date::DATE_R
• lp_timer::date::DATE_W
• lp_timer::date::R
• lp_timer::date::W
• lp_timer::int_clr::OVERFLOW_W
• lp_timer::int_clr::SOC_WAKEUP_W
• lp_timer::int_clr::W
• lp_timer::int_ena::OVERFLOW_R
• lp_timer::int_ena::OVERFLOW_W
• lp_timer::int_ena::R
• lp_timer::int_ena::SOC_WAKEUP_R
• lp_timer::int_ena::SOC_WAKEUP_W
• lp_timer::int_ena::W
• lp_timer::int_raw::OVERFLOW_R
• lp_timer::int_raw::OVERFLOW_W
• lp_timer::int_raw::R
• lp_timer::int_raw::SOC_WAKEUP_R
• lp_timer::int_raw::SOC_WAKEUP_W
• lp_timer::int_raw::W
• lp_timer::int_st::OVERFLOW_R
• lp_timer::int_st::R
• lp_timer::int_st::SOC_WAKEUP_R
• lp_timer::lp_int_clr::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_clr::MAIN_TIMER_W
• lp_timer::lp_int_clr::W
• lp_timer::lp_int_ena::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_ena::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_ena::MAIN_TIMER_R
• lp_timer::lp_int_ena::MAIN_TIMER_W
• lp_timer::lp_int_ena::R
• lp_timer::lp_int_ena::W
• lp_timer::lp_int_raw::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_raw::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_raw::MAIN_TIMER_R
• lp_timer::lp_int_raw::MAIN_TIMER_W
• lp_timer::lp_int_raw::R
• lp_timer::lp_int_raw::W
• lp_timer::lp_int_st::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_st::MAIN_TIMER_R
• lp_timer::lp_int_st::R
• lp_timer::main_buf0_high::MAIN_TIMER_BUF0_HIGH_R
• lp_timer::main_buf0_high::R
• lp_timer::main_buf0_low::MAIN_TIMER_BUF0_LOW_R
• lp_timer::main_buf0_low::R
• lp_timer::main_buf1_high::MAIN_TIMER_BUF1_HIGH_R
• lp_timer::main_buf1_high::R
• lp_timer::main_buf1_low::MAIN_TIMER_BUF1_LOW_R
• lp_timer::main_buf1_low::R
• lp_timer::main_overflow::MAIN_TIMER_ALARM_LOAD_W
• lp_timer::main_overflow::W
• lp_timer::tar0_high::MAIN_TIMER_TAR_EN0_W
• lp_timer::tar0_high::MAIN_TIMER_TAR_HIGH0_R
• lp_timer::tar0_high::MAIN_TIMER_TAR_HIGH0_W
• lp_timer::tar0_high::R
• lp_timer::tar0_high::W
• lp_timer::tar0_low::MAIN_TIMER_TAR_LOW0_R
• lp_timer::tar0_low::MAIN_TIMER_TAR_LOW0_W
• lp_timer::tar0_low::R
• lp_timer::tar0_low::W
• lp_timer::tar1_high::MAIN_TIMER_TAR_EN1_W
• lp_timer::tar1_high::MAIN_TIMER_TAR_HIGH1_R
• lp_timer::tar1_high::MAIN_TIMER_TAR_HIGH1_W
• lp_timer::tar1_high::R
• lp_timer::tar1_high::W
• lp_timer::tar1_low::MAIN_TIMER_TAR_LOW1_R
• lp_timer::tar1_low::MAIN_TIMER_TAR_LOW1_W
• lp_timer::tar1_low::R
• lp_timer::tar1_low::W
• lp_timer::update::MAIN_TIMER_SYS_RST_R
• lp_timer::update::MAIN_TIMER_SYS_RST_W
• lp_timer::update::MAIN_TIMER_SYS_STALL_R
• lp_timer::update::MAIN_TIMER_SYS_STALL_W
• lp_timer::update::MAIN_TIMER_UPDATE_W
• lp_timer::update::MAIN_TIMER_XTAL_OFF_R
• lp_timer::update::MAIN_TIMER_XTAL_OFF_W
• lp_timer::update::R
• lp_timer::update::W
• lp_uart::AFIFO_STATUS
• lp_uart::AT_CMD_CHAR_SYNC
• lp_uart::AT_CMD_GAPTOUT_SYNC
• lp_uart::AT_CMD_POSTCNT_SYNC
• lp_uart::AT_CMD_PRECNT_SYNC
• lp_uart::CLKDIV_SYNC
• lp_uart::CLK_CONF
• lp_uart::CONF0_SYNC
• lp_uart::CONF1
• lp_uart::DATE
• lp_uart::FIFO
• lp_uart::FSM_STATUS
• lp_uart::HWFC_CONF_SYNC
• lp_uart::ID
• lp_uart::IDLE_CONF_SYNC
• lp_uart::INT_CLR
• lp_uart::INT_ENA
• lp_uart::INT_RAW
• lp_uart::INT_ST
• lp_uart::MEM_CONF
• lp_uart::MEM_RX_STATUS
• lp_uart::MEM_TX_STATUS
• lp_uart::REG_UPDATE
• lp_uart::RS485_CONF_SYNC
• lp_uart::RX_FILT
• lp_uart::SLEEP_CONF0
• lp_uart::SLEEP_CONF1
• lp_uart::SLEEP_CONF2
• lp_uart::STATUS
• lp_uart::SWFC_CONF0_SYNC
• lp_uart::SWFC_CONF1
• lp_uart::TOUT_CONF_SYNC
• lp_uart::TXBRK_CONF_SYNC
• lp_uart::afifo_status::R
• lp_uart::afifo_status::RX_AFIFO_EMPTY_R
• lp_uart::afifo_status::RX_AFIFO_FULL_R
• lp_uart::afifo_status::TX_AFIFO_EMPTY_R
• lp_uart::afifo_status::TX_AFIFO_FULL_R
• lp_uart::at_cmd_char_sync::AT_CMD_CHAR_R
• lp_uart::at_cmd_char_sync::AT_CMD_CHAR_W
• lp_uart::at_cmd_char_sync::CHAR_NUM_R
• lp_uart::at_cmd_char_sync::CHAR_NUM_W
• lp_uart::at_cmd_char_sync::R
• lp_uart::at_cmd_char_sync::W
• lp_uart::at_cmd_gaptout_sync::R
• lp_uart::at_cmd_gaptout_sync::RX_GAP_TOUT_R
• lp_uart::at_cmd_gaptout_sync::RX_GAP_TOUT_W
• lp_uart::at_cmd_gaptout_sync::W
• lp_uart::at_cmd_postcnt_sync::POST_IDLE_NUM_R
• lp_uart::at_cmd_postcnt_sync::POST_IDLE_NUM_W
• lp_uart::at_cmd_postcnt_sync::R
• lp_uart::at_cmd_postcnt_sync::W
• lp_uart::at_cmd_precnt_sync::PRE_IDLE_NUM_R
• lp_uart::at_cmd_precnt_sync::PRE_IDLE_NUM_W
• lp_uart::at_cmd_precnt_sync::R
• lp_uart::at_cmd_precnt_sync::W
• lp_uart::clk_conf::R
• lp_uart::clk_conf::RST_CORE_R
• lp_uart::clk_conf::RST_CORE_W
• lp_uart::clk_conf::RX_RST_CORE_R
• lp_uart::clk_conf::RX_RST_CORE_W
• lp_uart::clk_conf::RX_SCLK_EN_R
• lp_uart::clk_conf::RX_SCLK_EN_W
• lp_uart::clk_conf::SCLK_DIV_A_R
• lp_uart::clk_conf::SCLK_DIV_A_W
• lp_uart::clk_conf::SCLK_DIV_B_R
• lp_uart::clk_conf::SCLK_DIV_B_W
• lp_uart::clk_conf::SCLK_DIV_NUM_R
• lp_uart::clk_conf::SCLK_DIV_NUM_W
• lp_uart::clk_conf::SCLK_EN_R
• lp_uart::clk_conf::SCLK_EN_W
• lp_uart::clk_conf::SCLK_SEL_R
• lp_uart::clk_conf::SCLK_SEL_W
• lp_uart::clk_conf::TX_RST_CORE_R
• lp_uart::clk_conf::TX_RST_CORE_W
• lp_uart::clk_conf::TX_SCLK_EN_R
• lp_uart::clk_conf::TX_SCLK_EN_W
• lp_uart::clk_conf::W
• lp_uart::clkdiv_sync::CLKDIV_FRAG_R
• lp_uart::clkdiv_sync::CLKDIV_FRAG_W
• lp_uart::clkdiv_sync::CLKDIV_R
• lp_uart::clkdiv_sync::CLKDIV_W
• lp_uart::clkdiv_sync::R
• lp_uart::clkdiv_sync::W
• lp_uart::conf0_sync::BIT_NUM_R
• lp_uart::conf0_sync::BIT_NUM_W
• lp_uart::conf0_sync::DIS_RX_DAT_OVF_R
• lp_uart::conf0_sync::DIS_RX_DAT_OVF_W
• lp_uart::conf0_sync::ERR_WR_MASK_R
• lp_uart::conf0_sync::ERR_WR_MASK_W
• lp_uart::conf0_sync::LOOPBACK_R
• lp_uart::conf0_sync::LOOPBACK_W
• lp_uart::conf0_sync::MEM_CLK_EN_R
• lp_uart::conf0_sync::MEM_CLK_EN_W
• lp_uart::conf0_sync::PARITY_EN_R
• lp_uart::conf0_sync::PARITY_EN_W
• lp_uart::conf0_sync::PARITY_R
• lp_uart::conf0_sync::PARITY_W
• lp_uart::conf0_sync::R
• lp_uart::conf0_sync::RXD_INV_R
• lp_uart::conf0_sync::RXD_INV_W
• lp_uart::conf0_sync::RXFIFO_RST_R
• lp_uart::conf0_sync::RXFIFO_RST_W
• lp_uart::conf0_sync::STOP_BIT_NUM_R
• lp_uart::conf0_sync::STOP_BIT_NUM_W
• lp_uart::conf0_sync::SW_RTS_R
• lp_uart::conf0_sync::SW_RTS_W
• lp_uart::conf0_sync::TXD_BRK_R
• lp_uart::conf0_sync::TXD_BRK_W
• lp_uart::conf0_sync::TXD_INV_R
• lp_uart::conf0_sync::TXD_INV_W
• lp_uart::conf0_sync::TXFIFO_RST_R
• lp_uart::conf0_sync::TXFIFO_RST_W
• lp_uart::conf0_sync::TX_FLOW_EN_R
• lp_uart::conf0_sync::TX_FLOW_EN_W
• lp_uart::conf0_sync::W
• lp_uart::conf1::CLK_EN_R
• lp_uart::conf1::CLK_EN_W
• lp_uart::conf1::CTS_INV_R
• lp_uart::conf1::CTS_INV_W
• lp_uart::conf1::DSR_INV_R
• lp_uart::conf1::DSR_INV_W
• lp_uart::conf1::DTR_INV_R
• lp_uart::conf1::DTR_INV_W
• lp_uart::conf1::R
• lp_uart::conf1::RTS_INV_R
• lp_uart::conf1::RTS_INV_W
• lp_uart::conf1::RXFIFO_FULL_THRHD_R
• lp_uart::conf1::RXFIFO_FULL_THRHD_W
• lp_uart::conf1::SW_DTR_R
• lp_uart::conf1::SW_DTR_W
• lp_uart::conf1::TXFIFO_EMPTY_THRHD_R
• lp_uart::conf1::TXFIFO_EMPTY_THRHD_W
• lp_uart::conf1::W
• lp_uart::date::DATE_R
• lp_uart::date::DATE_W
• lp_uart::date::R
• lp_uart::date::W
• lp_uart::fifo::R
• lp_uart::fifo::RXFIFO_RD_BYTE_R
• lp_uart::fifo::RXFIFO_RD_BYTE_W
• lp_uart::fifo::W
• lp_uart::fsm_status::R
• lp_uart::fsm_status::ST_URX_OUT_R
• lp_uart::fsm_status::ST_UTX_OUT_R
• lp_uart::hwfc_conf_sync::R
• lp_uart::hwfc_conf_sync::RX_FLOW_EN_R
• lp_uart::hwfc_conf_sync::RX_FLOW_EN_W
• lp_uart::hwfc_conf_sync::RX_FLOW_THRHD_R
• lp_uart::hwfc_conf_sync::RX_FLOW_THRHD_W
• lp_uart::hwfc_conf_sync::W
• lp_uart::id::ID_R
• lp_uart::id::ID_W
• lp_uart::id::R
• lp_uart::id::W
• lp_uart::idle_conf_sync::R
• lp_uart::idle_conf_sync::RX_IDLE_THRHD_R
• lp_uart::idle_conf_sync::RX_IDLE_THRHD_W
• lp_uart::idle_conf_sync::TX_IDLE_NUM_R
• lp_uart::idle_conf_sync::TX_IDLE_NUM_W
• lp_uart::idle_conf_sync::W
• lp_uart::int_clr::AT_CMD_CHAR_DET_W
• lp_uart::int_clr::BRK_DET_W
• lp_uart::int_clr::CTS_CHG_W
• lp_uart::int_clr::DSR_CHG_W
• lp_uart::int_clr::FRM_ERR_W
• lp_uart::int_clr::GLITCH_DET_W
• lp_uart::int_clr::PARITY_ERR_W
• lp_uart::int_clr::RXFIFO_FULL_W
• lp_uart::int_clr::RXFIFO_OVF_W
• lp_uart::int_clr::RXFIFO_TOUT_W
• lp_uart::int_clr::SW_XOFF_W
• lp_uart::int_clr::SW_XON_W
• lp_uart::int_clr::TXFIFO_EMPTY_W
• lp_uart::int_clr::TX_BRK_DONE_W
• lp_uart::int_clr::TX_BRK_IDLE_DONE_W
• lp_uart::int_clr::TX_DONE_W
• lp_uart::int_clr::W
• lp_uart::int_clr::WAKEUP_W
• lp_uart::int_ena::AT_CMD_CHAR_DET_R
• lp_uart::int_ena::AT_CMD_CHAR_DET_W
• lp_uart::int_ena::BRK_DET_R
• lp_uart::int_ena::BRK_DET_W
• lp_uart::int_ena::CTS_CHG_R
• lp_uart::int_ena::CTS_CHG_W
• lp_uart::int_ena::DSR_CHG_R
• lp_uart::int_ena::DSR_CHG_W
• lp_uart::int_ena::FRM_ERR_R
• lp_uart::int_ena::FRM_ERR_W
• lp_uart::int_ena::GLITCH_DET_R
• lp_uart::int_ena::GLITCH_DET_W
• lp_uart::int_ena::PARITY_ERR_R
• lp_uart::int_ena::PARITY_ERR_W
• lp_uart::int_ena::R
• lp_uart::int_ena::RXFIFO_FULL_R
• lp_uart::int_ena::RXFIFO_FULL_W
• lp_uart::int_ena::RXFIFO_OVF_R
• lp_uart::int_ena::RXFIFO_OVF_W
• lp_uart::int_ena::RXFIFO_TOUT_R
• lp_uart::int_ena::RXFIFO_TOUT_W
• lp_uart::int_ena::SW_XOFF_R
• lp_uart::int_ena::SW_XOFF_W
• lp_uart::int_ena::SW_XON_R
• lp_uart::int_ena::SW_XON_W
• lp_uart::int_ena::TXFIFO_EMPTY_R
• lp_uart::int_ena::TXFIFO_EMPTY_W
• lp_uart::int_ena::TX_BRK_DONE_R
• lp_uart::int_ena::TX_BRK_DONE_W
• lp_uart::int_ena::TX_BRK_IDLE_DONE_R
• lp_uart::int_ena::TX_BRK_IDLE_DONE_W
• lp_uart::int_ena::TX_DONE_R
• lp_uart::int_ena::TX_DONE_W
• lp_uart::int_ena::W
• lp_uart::int_ena::WAKEUP_R
• lp_uart::int_ena::WAKEUP_W
• lp_uart::int_raw::AT_CMD_CHAR_DET_R
• lp_uart::int_raw::AT_CMD_CHAR_DET_W
• lp_uart::int_raw::BRK_DET_R
• lp_uart::int_raw::BRK_DET_W
• lp_uart::int_raw::CTS_CHG_R
• lp_uart::int_raw::CTS_CHG_W
• lp_uart::int_raw::DSR_CHG_R
• lp_uart::int_raw::DSR_CHG_W
• lp_uart::int_raw::FRM_ERR_R
• lp_uart::int_raw::FRM_ERR_W
• lp_uart::int_raw::GLITCH_DET_R
• lp_uart::int_raw::GLITCH_DET_W
• lp_uart::int_raw::PARITY_ERR_R
• lp_uart::int_raw::PARITY_ERR_W
• lp_uart::int_raw::R
• lp_uart::int_raw::RXFIFO_FULL_R
• lp_uart::int_raw::RXFIFO_FULL_W
• lp_uart::int_raw::RXFIFO_OVF_R
• lp_uart::int_raw::RXFIFO_OVF_W
• lp_uart::int_raw::RXFIFO_TOUT_R
• lp_uart::int_raw::RXFIFO_TOUT_W
• lp_uart::int_raw::SW_XOFF_R
• lp_uart::int_raw::SW_XOFF_W
• lp_uart::int_raw::SW_XON_R
• lp_uart::int_raw::SW_XON_W
• lp_uart::int_raw::TXFIFO_EMPTY_R
• lp_uart::int_raw::TXFIFO_EMPTY_W
• lp_uart::int_raw::TX_BRK_DONE_R
• lp_uart::int_raw::TX_BRK_DONE_W
• lp_uart::int_raw::TX_BRK_IDLE_DONE_R
• lp_uart::int_raw::TX_BRK_IDLE_DONE_W
• lp_uart::int_raw::TX_DONE_R
• lp_uart::int_raw::TX_DONE_W
• lp_uart::int_raw::W
• lp_uart::int_raw::WAKEUP_R
• lp_uart::int_raw::WAKEUP_W
• lp_uart::int_st::AT_CMD_CHAR_DET_R
• lp_uart::int_st::BRK_DET_R
• lp_uart::int_st::CTS_CHG_R
• lp_uart::int_st::DSR_CHG_R
• lp_uart::int_st::FRM_ERR_R
• lp_uart::int_st::GLITCH_DET_R
• lp_uart::int_st::PARITY_ERR_R
• lp_uart::int_st::R
• lp_uart::int_st::RXFIFO_FULL_R
• lp_uart::int_st::RXFIFO_OVF_R
• lp_uart::int_st::RXFIFO_TOUT_R
• lp_uart::int_st::SW_XOFF_R
• lp_uart::int_st::SW_XON_R
• lp_uart::int_st::TXFIFO_EMPTY_R
• lp_uart::int_st::TX_BRK_DONE_R
• lp_uart::int_st::TX_BRK_IDLE_DONE_R
• lp_uart::int_st::TX_DONE_R
• lp_uart::int_st::WAKEUP_R
• lp_uart::mem_conf::MEM_FORCE_PD_R
• lp_uart::mem_conf::MEM_FORCE_PD_W
• lp_uart::mem_conf::MEM_FORCE_PU_R
• lp_uart::mem_conf::MEM_FORCE_PU_W
• lp_uart::mem_conf::R
• lp_uart::mem_conf::W
• lp_uart::mem_rx_status::R
• lp_uart::mem_rx_status::RX_SRAM_RADDR_R
• lp_uart::mem_rx_status::RX_SRAM_WADDR_R
• lp_uart::mem_tx_status::R
• lp_uart::mem_tx_status::TX_SRAM_RADDR_R
• lp_uart::mem_tx_status::TX_SRAM_WADDR_R
• lp_uart::reg_update::R
• lp_uart::reg_update::REG_UPDATE_R
• lp_uart::reg_update::REG_UPDATE_W
• lp_uart::reg_update::W
• lp_uart::rs485_conf_sync::DL0_EN_R
• lp_uart::rs485_conf_sync::DL0_EN_W
• lp_uart::rs485_conf_sync::DL1_EN_R
• lp_uart::rs485_conf_sync::DL1_EN_W
• lp_uart::rs485_conf_sync::R
• lp_uart::rs485_conf_sync::W
• lp_uart::rx_filt::GLITCH_FILT_EN_R
• lp_uart::rx_filt::GLITCH_FILT_EN_W
• lp_uart::rx_filt::GLITCH_FILT_R
• lp_uart::rx_filt::GLITCH_FILT_W
• lp_uart::rx_filt::R
• lp_uart::rx_filt::W
• lp_uart::sleep_conf0::R
• lp_uart::sleep_conf0::W
• lp_uart::sleep_conf0::WK_CHAR1_R
• lp_uart::sleep_conf0::WK_CHAR1_W
• lp_uart::sleep_conf0::WK_CHAR2_R
• lp_uart::sleep_conf0::WK_CHAR2_W
• lp_uart::sleep_conf0::WK_CHAR3_R
• lp_uart::sleep_conf0::WK_CHAR3_W
• lp_uart::sleep_conf0::WK_CHAR4_R
• lp_uart::sleep_conf0::WK_CHAR4_W
• lp_uart::sleep_conf1::R
• lp_uart::sleep_conf1::W
• lp_uart::sleep_conf1::WK_CHAR0_R
• lp_uart::sleep_conf1::WK_CHAR0_W
• lp_uart::sleep_conf2::ACTIVE_THRESHOLD_R
• lp_uart::sleep_conf2::ACTIVE_THRESHOLD_W
• lp_uart::sleep_conf2::R
• lp_uart::sleep_conf2::RX_WAKE_UP_THRHD_R
• lp_uart::sleep_conf2::RX_WAKE_UP_THRHD_W
• lp_uart::sleep_conf2::W
• lp_uart::sleep_conf2::WK_CHAR_MASK_R
• lp_uart::sleep_conf2::WK_CHAR_MASK_W
• lp_uart::sleep_conf2::WK_CHAR_NUM_R
• lp_uart::sleep_conf2::WK_CHAR_NUM_W
• lp_uart::sleep_conf2::WK_MODE_SEL_R
• lp_uart::sleep_conf2::WK_MODE_SEL_W
• lp_uart::status::CTSN_R
• lp_uart::status::DSRN_R
• lp_uart::status::DTRN_R
• lp_uart::status::R
• lp_uart::status::RTSN_R
• lp_uart::status::RXD_R
• lp_uart::status::RXFIFO_CNT_R
• lp_uart::status::TXD_R
• lp_uart::status::TXFIFO_CNT_R
• lp_uart::swfc_conf0_sync::FORCE_XOFF_R
• lp_uart::swfc_conf0_sync::FORCE_XOFF_W
• lp_uart::swfc_conf0_sync::FORCE_XON_R
• lp_uart::swfc_conf0_sync::FORCE_XON_W
• lp_uart::swfc_conf0_sync::R
• lp_uart::swfc_conf0_sync::SEND_XOFF_R
• lp_uart::swfc_conf0_sync::SEND_XOFF_W
• lp_uart::swfc_conf0_sync::SEND_XON_R
• lp_uart::swfc_conf0_sync::SEND_XON_W
• lp_uart::swfc_conf0_sync::SW_FLOW_CON_EN_R
• lp_uart::swfc_conf0_sync::SW_FLOW_CON_EN_W
• lp_uart::swfc_conf0_sync::W
• lp_uart::swfc_conf0_sync::XOFF_CHAR_R
• lp_uart::swfc_conf0_sync::XOFF_CHAR_W
• lp_uart::swfc_conf0_sync::XONOFF_DEL_R
• lp_uart::swfc_conf0_sync::XONOFF_DEL_W
• lp_uart::swfc_conf0_sync::XON_CHAR_R
• lp_uart::swfc_conf0_sync::XON_CHAR_W
• lp_uart::swfc_conf0_sync::XON_XOFF_STILL_SEND_R
• lp_uart::swfc_conf0_sync::XON_XOFF_STILL_SEND_W
• lp_uart::swfc_conf1::R
• lp_uart::swfc_conf1::W
• lp_uart::swfc_conf1::XOFF_THRESHOLD_R
• lp_uart::swfc_conf1::XOFF_THRESHOLD_W
• lp_uart::swfc_conf1::XON_THRESHOLD_R
• lp_uart::swfc_conf1::XON_THRESHOLD_W
• lp_uart::tout_conf_sync::R
• lp_uart::tout_conf_sync::RX_TOUT_EN_R
• lp_uart::tout_conf_sync::RX_TOUT_EN_W
• lp_uart::tout_conf_sync::RX_TOUT_FLOW_DIS_R
• lp_uart::tout_conf_sync::RX_TOUT_FLOW_DIS_W
• lp_uart::tout_conf_sync::RX_TOUT_THRHD_R
• lp_uart::tout_conf_sync::RX_TOUT_THRHD_W
• lp_uart::tout_conf_sync::W
• lp_uart::txbrk_conf_sync::R
• lp_uart::txbrk_conf_sync::TX_BRK_NUM_R
• lp_uart::txbrk_conf_sync::TX_BRK_NUM_W
• lp_uart::txbrk_conf_sync::W
• lp_wdt::CONFIG0
• lp_wdt::CONFIG1
• lp_wdt::CONFIG2
• lp_wdt::CONFIG3
• lp_wdt::CONFIG4
• lp_wdt::DATE
• lp_wdt::FEED
• lp_wdt::INT_CLR
• lp_wdt::INT_ENA
• lp_wdt::INT_RAW
• lp_wdt::INT_ST
• lp_wdt::SWD_CONFIG
• lp_wdt::SWD_WPROTECT
• lp_wdt::WPROTECT
• lp_wdt::config0::R
• lp_wdt::config0::W
• lp_wdt::config0::WDT_APPCPU_RESET_EN_R
• lp_wdt::config0::WDT_APPCPU_RESET_EN_W
• lp_wdt::config0::WDT_CHIP_RESET_EN_R
• lp_wdt::config0::WDT_CHIP_RESET_EN_W
• lp_wdt::config0::WDT_CHIP_RESET_WIDTH_R
• lp_wdt::config0::WDT_CHIP_RESET_WIDTH_W
• lp_wdt::config0::WDT_CPU_RESET_LENGTH_R
• lp_wdt::config0::WDT_CPU_RESET_LENGTH_W
• lp_wdt::config0::WDT_EN_R
• lp_wdt::config0::WDT_EN_W
• lp_wdt::config0::WDT_FLASHBOOT_MOD_EN_R
• lp_wdt::config0::WDT_FLASHBOOT_MOD_EN_W
• lp_wdt::config0::WDT_PAUSE_IN_SLP_R
• lp_wdt::config0::WDT_PAUSE_IN_SLP_W
• lp_wdt::config0::WDT_PROCPU_RESET_EN_R
• lp_wdt::config0::WDT_PROCPU_RESET_EN_W
• lp_wdt::config0::WDT_STG0_R
• lp_wdt::config0::WDT_STG0_W
• lp_wdt::config0::WDT_STG1_R
• lp_wdt::config0::WDT_STG1_W
• lp_wdt::config0::WDT_STG2_R
• lp_wdt::config0::WDT_STG2_W
• lp_wdt::config0::WDT_STG3_R
• lp_wdt::config0::WDT_STG3_W
• lp_wdt::config0::WDT_SYS_RESET_LENGTH_R
• lp_wdt::config0::WDT_SYS_RESET_LENGTH_W
• lp_wdt::config1::R
• lp_wdt::config1::W
• lp_wdt::config1::WDT_STG0_HOLD_R
• lp_wdt::config1::WDT_STG0_HOLD_W
• lp_wdt::config2::R
• lp_wdt::config2::W
• lp_wdt::config2::WDT_STG1_HOLD_R
• lp_wdt::config2::WDT_STG1_HOLD_W
• lp_wdt::config3::R
• lp_wdt::config3::W
• lp_wdt::config3::WDT_STG2_HOLD_R
• lp_wdt::config3::WDT_STG2_HOLD_W
• lp_wdt::config4::R
• lp_wdt::config4::W
• lp_wdt::config4::WDT_STG3_HOLD_R
• lp_wdt::config4::WDT_STG3_HOLD_W
• lp_wdt::date::CLK_EN_R
• lp_wdt::date::CLK_EN_W
• lp_wdt::date::LP_WDT_DATE_R
• lp_wdt::date::LP_WDT_DATE_W
• lp_wdt::date::R
• lp_wdt::date::W
• lp_wdt::feed::RTC_WDT_FEED_W
• lp_wdt::feed::W
• lp_wdt::int_clr::LP_WDT_W
• lp_wdt::int_clr::SUPER_WDT_W
• lp_wdt::int_clr::W
• lp_wdt::int_ena::LP_WDT_R
• lp_wdt::int_ena::LP_WDT_W
• lp_wdt::int_ena::R
• lp_wdt::int_ena::SUPER_WDT_R
• lp_wdt::int_ena::SUPER_WDT_W
• lp_wdt::int_ena::W
• lp_wdt::int_raw::LP_WDT_R
• lp_wdt::int_raw::LP_WDT_W
• lp_wdt::int_raw::R
• lp_wdt::int_raw::SUPER_WDT_R
• lp_wdt::int_raw::SUPER_WDT_W
• lp_wdt::int_raw::W
• lp_wdt::int_st::LP_WDT_R
• lp_wdt::int_st::R
• lp_wdt::int_st::SUPER_WDT_R
• lp_wdt::swd_config::R
• lp_wdt::swd_config::SWD_AUTO_FEED_EN_R
• lp_wdt::swd_config::SWD_AUTO_FEED_EN_W
• lp_wdt::swd_config::SWD_DISABLE_R
• lp_wdt::swd_config::SWD_DISABLE_W
• lp_wdt::swd_config::SWD_FEED_W
• lp_wdt::swd_config::SWD_RESET_FLAG_R
• lp_wdt::swd_config::SWD_RST_FLAG_CLR_W
• lp_wdt::swd_config::SWD_SIGNAL_WIDTH_R
• lp_wdt::swd_config::SWD_SIGNAL_WIDTH_W
• lp_wdt::swd_config::W
• lp_wdt::swd_wprotect::R
• lp_wdt::swd_wprotect::SWD_WKEY_R
• lp_wdt::swd_wprotect::SWD_WKEY_W
• lp_wdt::swd_wprotect::W
• lp_wdt::wprotect::R
• lp_wdt::wprotect::W
• lp_wdt::wprotect::WDT_WKEY_R
• lp_wdt::wprotect::WDT_WKEY_W
• pmu::BACKUP_CFG
• pmu::CLK_STATE0
• pmu::CLK_STATE1
• pmu::CLK_STATE2
• pmu::DATE
• pmu::HP_ACTIVE_BACKUP
• pmu::HP_ACTIVE_BACKUP_CLK
• pmu::HP_ACTIVE_BIAS
• pmu::HP_ACTIVE_DIG_POWER
• pmu::HP_ACTIVE_HP_CK_POWER
• pmu::HP_ACTIVE_HP_REGULATOR0
• pmu::HP_ACTIVE_HP_REGULATOR1
• pmu::HP_ACTIVE_HP_SYS_CNTL
• pmu::HP_ACTIVE_ICG_HP_APB
• pmu::HP_ACTIVE_ICG_HP_FUNC
• pmu::HP_ACTIVE_ICG_MODEM
• pmu::HP_ACTIVE_SYSCLK
• pmu::HP_ACTIVE_XTAL
• pmu::HP_CK_CNTL
• pmu::HP_CK_POWERON
• pmu::HP_LP_CPU_COMM
• pmu::HP_MODEM_BACKUP
• pmu::HP_MODEM_BACKUP_CLK
• pmu::HP_MODEM_BIAS
• pmu::HP_MODEM_DIG_POWER
• pmu::HP_MODEM_HP_CK_POWER
• pmu::HP_MODEM_HP_REGULATOR0
• pmu::HP_MODEM_HP_REGULATOR1
• pmu::HP_MODEM_HP_SYS_CNTL
• pmu::HP_MODEM_ICG_HP_APB
• pmu::HP_MODEM_ICG_HP_FUNC
• pmu::HP_MODEM_ICG_MODEM
• pmu::HP_MODEM_SYSCLK
• pmu::HP_MODEM_XTAL
• pmu::HP_REGULATOR_CFG
• pmu::HP_SLEEP_BACKUP
• pmu::HP_SLEEP_BACKUP_CLK
• pmu::HP_SLEEP_BIAS
• pmu::HP_SLEEP_DIG_POWER
• pmu::HP_SLEEP_HP_CK_POWER
• pmu::HP_SLEEP_HP_REGULATOR0
• pmu::HP_SLEEP_HP_REGULATOR1
• pmu::HP_SLEEP_HP_SYS_CNTL
• pmu::HP_SLEEP_ICG_HP_APB
• pmu::HP_SLEEP_ICG_HP_FUNC
• pmu::HP_SLEEP_ICG_MODEM
• pmu::HP_SLEEP_LP_CK_POWER
• pmu::HP_SLEEP_LP_DCDC_RESERVE
• pmu::HP_SLEEP_LP_DIG_POWER
• pmu::HP_SLEEP_LP_REGULATOR0
• pmu::HP_SLEEP_LP_REGULATOR1
• pmu::HP_SLEEP_SYSCLK
• pmu::HP_SLEEP_XTAL
• pmu::IMM_HP_APB_ICG
• pmu::IMM_HP_CK_POWER
• pmu::IMM_HP_FUNC_ICG
• pmu::IMM_I2C_ISO
• pmu::IMM_LP_ICG
• pmu::IMM_MODEM_ICG
• pmu::IMM_PAD_HOLD_ALL
• pmu::IMM_SLEEP_SYSCLK
• pmu::INT_CLR
• pmu::INT_ENA
• pmu::INT_RAW
• pmu::INT_ST
• pmu::LP_CPU_PWR0
• pmu::LP_CPU_PWR1
• pmu::LP_INT_CLR
• pmu::LP_INT_ENA
• pmu::LP_INT_RAW
• pmu::LP_INT_ST
• pmu::LP_SLEEP_BIAS
• pmu::LP_SLEEP_LP_BIAS_RESERVE
• pmu::LP_SLEEP_LP_CK_POWER
• pmu::LP_SLEEP_LP_DIG_POWER
• pmu::LP_SLEEP_LP_REGULATOR0
• pmu::LP_SLEEP_LP_REGULATOR1
• pmu::LP_SLEEP_XTAL
• pmu::MAIN_STATE
• pmu::POR_STATUS
• pmu::POWER_CK_WAIT_CNTL
• pmu::POWER_HP_PAD
• pmu::POWER_PD_HPAON_CNTL
• pmu::POWER_PD_HPCPU_CNTL
• pmu::POWER_PD_HPPERI_RESERVE
• pmu::POWER_PD_HPWIFI_CNTL
• pmu::POWER_PD_LPPERI_CNTL
• pmu::POWER_PD_MEM_CNTL
• pmu::POWER_PD_MEM_MASK
• pmu::POWER_PD_TOP_CNTL
• pmu::POWER_VDD_SPI_CNTL
• pmu::POWER_WAIT_TIMER0
• pmu::POWER_WAIT_TIMER1
• pmu::PWR_STATE
• pmu::RF_PWC
• pmu::SLP_WAKEUP_CNTL0
• pmu::SLP_WAKEUP_CNTL1
• pmu::SLP_WAKEUP_CNTL2
• pmu::SLP_WAKEUP_CNTL3
• pmu::SLP_WAKEUP_CNTL4
• pmu::SLP_WAKEUP_CNTL5
• pmu::SLP_WAKEUP_CNTL6
• pmu::SLP_WAKEUP_CNTL7
• pmu::SLP_WAKEUP_STATUS0
• pmu::SLP_WAKEUP_STATUS1
• pmu::VDD_SPI_STATUS
• pmu::backup_cfg::BACKUP_SYS_CLK_NO_DIV_R
• pmu::backup_cfg::BACKUP_SYS_CLK_NO_DIV_W
• pmu::backup_cfg::R
• pmu::backup_cfg::W
• pmu::clk_state0::ANA_I2C_ISO_EN_STATE_R
• pmu::clk_state0::ANA_I2C_RETENTION_STATE_R
• pmu::clk_state0::ANA_XPD_BBPLL_I2C_STATE_R
• pmu::clk_state0::ANA_XPD_BBPLL_STATE_R
• pmu::clk_state0::ANA_XPD_BB_I2C_STATE_R
• pmu::clk_state0::ANA_XPD_XTAL_STATE_R
• pmu::clk_state0::ICG_GLOBAL_PLL_STATE_R
• pmu::clk_state0::ICG_GLOBAL_XTAL_STATE_R
• pmu::clk_state0::ICG_MODEM_CODE_STATE_R
• pmu::clk_state0::ICG_MODEM_SWITCH_STATE_R
• pmu::clk_state0::ICG_SLP_SEL_STATE_R
• pmu::clk_state0::ICG_SYS_CLK_EN_STATE_R
• pmu::clk_state0::R
• pmu::clk_state0::STABLE_XPD_BBPLL_STATE_R
• pmu::clk_state0::STABLE_XPD_XTAL_STATE_R
• pmu::clk_state0::SYS_CLK_NO_DIV_STATE_R
• pmu::clk_state0::SYS_CLK_SEL_STATE_R
• pmu::clk_state0::SYS_CLK_SLP_SEL_STATE_R
• pmu::clk_state1::ICG_FUNC_EN_STATE_R
• pmu::clk_state1::R
• pmu::clk_state2::ICG_APB_EN_STATE_R
• pmu::clk_state2::R
• pmu::date::CLK_EN_R
• pmu::date::CLK_EN_W
• pmu::date::PMU_DATE_R
• pmu::date::PMU_DATE_W
• pmu::date::R
• pmu::date::W
• pmu::hp_active_backup::HP_ACTIVE_RETENTION_MODE_R
• pmu::hp_active_backup::HP_ACTIVE_RETENTION_MODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_CLK_SEL_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_CLK_SEL_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_EN_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_EN_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODE_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_RETENTION_EN_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_RETENTION_EN_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_EN_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_EN_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODE_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODE_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_RETENTION_EN_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_RETENTION_EN_W
• pmu::hp_active_backup::R
• pmu::hp_active_backup::W
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_ICG_FUNC_EN_R
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_ICG_FUNC_EN_W
• pmu::hp_active_backup_clk::R
• pmu::hp_active_backup_clk::W
• pmu::hp_active_bias::HP_ACTIVE_DBG_ATTEN_R
• pmu::hp_active_bias::HP_ACTIVE_DBG_ATTEN_W
• pmu::hp_active_bias::HP_ACTIVE_PD_CUR_R
• pmu::hp_active_bias::HP_ACTIVE_PD_CUR_W
• pmu::hp_active_bias::HP_ACTIVE_XPD_BIAS_R
• pmu::hp_active_bias::HP_ACTIVE_XPD_BIAS_W
• pmu::hp_active_bias::R
• pmu::hp_active_bias::SLEEP_R
• pmu::hp_active_bias::SLEEP_W
• pmu::hp_active_bias::W
• pmu::hp_active_dig_power::HP_ACTIVE_HP_MEM_DSLP_R
• pmu::hp_active_dig_power::HP_ACTIVE_HP_MEM_DSLP_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_AON_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_AON_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_CPU_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_CPU_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_MEM_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_MEM_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_WIFI_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_WIFI_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_TOP_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_TOP_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_VDD_SPI_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_VDD_SPI_PD_EN_W
• pmu::hp_active_dig_power::R
• pmu::hp_active_dig_power::W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_ISO_EN_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_ISO_EN_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_RETENTION_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_RETENTION_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_I2C_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_I2C_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BB_I2C_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BB_I2C_W
• pmu::hp_active_hp_ck_power::R
• pmu::hp_active_hp_ck_power::W
• pmu::hp_active_hp_regulator0::DIG_DBIAS_INIT_W
• pmu::hp_active_hp_regulator0::DIG_REGULATOR0_DBIAS_SEL_R
• pmu::hp_active_hp_regulator0::DIG_REGULATOR0_DBIAS_SEL_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_XPD_W
• pmu::hp_active_hp_regulator0::HP_DBIAS_VOL_R
• pmu::hp_active_hp_regulator0::LP_DBIAS_VOL_R
• pmu::hp_active_hp_regulator0::R
• pmu::hp_active_hp_regulator0::W
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR_DRV_B_R
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR_DRV_B_W
• pmu::hp_active_hp_regulator1::R
• pmu::hp_active_hp_regulator1::W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_CPU_STALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_CPU_STALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAD_SLP_SEL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAD_SLP_SEL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAUSE_WDT_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAUSE_WDT_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_PAD_HOLD_ALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_PAD_HOLD_ALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_LP_PAD_HOLD_ALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_LP_PAD_HOLD_ALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_UART_WAKEUP_EN_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_UART_WAKEUP_EN_W
• pmu::hp_active_hp_sys_cntl::R
• pmu::hp_active_hp_sys_cntl::W
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_DIG_ICG_APB_EN_R
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_DIG_ICG_APB_EN_W
• pmu::hp_active_icg_hp_apb::R
• pmu::hp_active_icg_hp_apb::W
• pmu::hp_active_icg_hp_func::HP_ACTIVE_DIG_ICG_FUNC_EN_R
• pmu::hp_active_icg_hp_func::HP_ACTIVE_DIG_ICG_FUNC_EN_W
• pmu::hp_active_icg_hp_func::R
• pmu::hp_active_icg_hp_func::W
• pmu::hp_active_icg_modem::HP_ACTIVE_DIG_ICG_MODEM_CODE_R
• pmu::hp_active_icg_modem::HP_ACTIVE_DIG_ICG_MODEM_CODE_W
• pmu::hp_active_icg_modem::R
• pmu::hp_active_icg_modem::W
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_SEL_W
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SLP_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SLP_SEL_W
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SYS_CLOCK_EN_R
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SYS_CLOCK_EN_W
• pmu::hp_active_sysclk::HP_ACTIVE_SYS_CLK_SLP_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_SYS_CLK_SLP_SEL_W
• pmu::hp_active_sysclk::R
• pmu::hp_active_sysclk::W
• pmu::hp_active_xtal::HP_ACTIVE_XPD_XTAL_R
• pmu::hp_active_xtal::HP_ACTIVE_XPD_XTAL_W
• pmu::hp_active_xtal::R
• pmu::hp_active_xtal::W
• pmu::hp_ck_cntl::MODIFY_ICG_CNTL_WAIT_R
• pmu::hp_ck_cntl::MODIFY_ICG_CNTL_WAIT_W
• pmu::hp_ck_cntl::R
• pmu::hp_ck_cntl::SWITCH_ICG_CNTL_WAIT_R
• pmu::hp_ck_cntl::SWITCH_ICG_CNTL_WAIT_W
• pmu::hp_ck_cntl::W
• pmu::hp_ck_poweron::I2C_POR_WAIT_TARGET_R
• pmu::hp_ck_poweron::I2C_POR_WAIT_TARGET_W
• pmu::hp_ck_poweron::R
• pmu::hp_ck_poweron::W
• pmu::hp_lp_cpu_comm::HP_TRIGGER_LP_W
• pmu::hp_lp_cpu_comm::LP_TRIGGER_HP_W
• pmu::hp_lp_cpu_comm::W
• pmu::hp_modem_backup::HP_MODEM_RETENTION_MODE_R
• pmu::hp_modem_backup::HP_MODEM_RETENTION_MODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_CLK_SEL_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_CLK_SEL_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_EN_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_EN_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODE_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_RETENTION_EN_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_RETENTION_EN_W
• pmu::hp_modem_backup::R
• pmu::hp_modem_backup::W
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_ICG_FUNC_EN_R
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_ICG_FUNC_EN_W
• pmu::hp_modem_backup_clk::R
• pmu::hp_modem_backup_clk::W
• pmu::hp_modem_bias::HP_MODEM_DBG_ATTEN_R
• pmu::hp_modem_bias::HP_MODEM_DBG_ATTEN_W
• pmu::hp_modem_bias::HP_MODEM_PD_CUR_R
• pmu::hp_modem_bias::HP_MODEM_PD_CUR_W
• pmu::hp_modem_bias::HP_MODEM_XPD_BIAS_R
• pmu::hp_modem_bias::HP_MODEM_XPD_BIAS_W
• pmu::hp_modem_bias::R
• pmu::hp_modem_bias::SLEEP_R
• pmu::hp_modem_bias::SLEEP_W
• pmu::hp_modem_bias::W
• pmu::hp_modem_dig_power::HP_MODEM_HP_MEM_DSLP_R
• pmu::hp_modem_dig_power::HP_MODEM_HP_MEM_DSLP_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_AON_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_AON_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_CPU_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_CPU_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_MEM_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_MEM_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_WIFI_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_WIFI_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_TOP_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_TOP_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_VDD_SPI_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_VDD_SPI_PD_EN_W
• pmu::hp_modem_dig_power::R
• pmu::hp_modem_dig_power::W
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_ISO_EN_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_ISO_EN_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_RETENTION_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_RETENTION_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_I2C_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_I2C_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BB_I2C_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BB_I2C_W
• pmu::hp_modem_hp_ck_power::R
• pmu::hp_modem_hp_ck_power::W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_XPD_W
• pmu::hp_modem_hp_regulator0::R
• pmu::hp_modem_hp_regulator0::W
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR_DRV_B_R
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR_DRV_B_W
• pmu::hp_modem_hp_regulator1::R
• pmu::hp_modem_hp_regulator1::W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_CPU_STALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_CPU_STALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAD_SLP_SEL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAD_SLP_SEL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAUSE_WDT_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAUSE_WDT_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_PAD_HOLD_ALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_PAD_HOLD_ALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_LP_PAD_HOLD_ALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_LP_PAD_HOLD_ALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_UART_WAKEUP_EN_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_UART_WAKEUP_EN_W
• pmu::hp_modem_hp_sys_cntl::R
• pmu::hp_modem_hp_sys_cntl::W
• pmu::hp_modem_icg_hp_apb::HP_MODEM_DIG_ICG_APB_EN_R
• pmu::hp_modem_icg_hp_apb::HP_MODEM_DIG_ICG_APB_EN_W
• pmu::hp_modem_icg_hp_apb::R
• pmu::hp_modem_icg_hp_apb::W
• pmu::hp_modem_icg_hp_func::HP_MODEM_DIG_ICG_FUNC_EN_R
• pmu::hp_modem_icg_hp_func::HP_MODEM_DIG_ICG_FUNC_EN_W
• pmu::hp_modem_icg_hp_func::R
• pmu::hp_modem_icg_hp_func::W
• pmu::hp_modem_icg_modem::HP_MODEM_DIG_ICG_MODEM_CODE_R
• pmu::hp_modem_icg_modem::HP_MODEM_DIG_ICG_MODEM_CODE_W
• pmu::hp_modem_icg_modem::R
• pmu::hp_modem_icg_modem::W
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_SEL_W
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SLP_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SLP_SEL_W
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SYS_CLOCK_EN_R
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SYS_CLOCK_EN_W
• pmu::hp_modem_sysclk::HP_MODEM_SYS_CLK_SLP_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_SYS_CLK_SLP_SEL_W
• pmu::hp_modem_sysclk::R
• pmu::hp_modem_sysclk::W
• pmu::hp_modem_xtal::HP_MODEM_XPD_XTAL_R
• pmu::hp_modem_xtal::HP_MODEM_XPD_XTAL_W
• pmu::hp_modem_xtal::R
• pmu::hp_modem_xtal::W
• pmu::hp_regulator_cfg::DIG_REGULATOR_EN_CAL_R
• pmu::hp_regulator_cfg::DIG_REGULATOR_EN_CAL_W
• pmu::hp_regulator_cfg::R
• pmu::hp_regulator_cfg::W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_EN_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_EN_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODE_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODE_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_RETENTION_EN_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_RETENTION_EN_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_CLK_SEL_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_CLK_SEL_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_EN_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_EN_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODE_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODE_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_RETENTION_EN_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_RETENTION_EN_W
• pmu::hp_sleep_backup::HP_SLEEP_RETENTION_MODE_R
• pmu::hp_sleep_backup::HP_SLEEP_RETENTION_MODE_W
• pmu::hp_sleep_backup::R
• pmu::hp_sleep_backup::W
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_ICG_FUNC_EN_R
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_ICG_FUNC_EN_W
• pmu::hp_sleep_backup_clk::R
• pmu::hp_sleep_backup_clk::W
• pmu::hp_sleep_bias::HP_SLEEP_DBG_ATTEN_R
• pmu::hp_sleep_bias::HP_SLEEP_DBG_ATTEN_W
• pmu::hp_sleep_bias::HP_SLEEP_PD_CUR_R
• pmu::hp_sleep_bias::HP_SLEEP_PD_CUR_W
• pmu::hp_sleep_bias::HP_SLEEP_XPD_BIAS_R
• pmu::hp_sleep_bias::HP_SLEEP_XPD_BIAS_W
• pmu::hp_sleep_bias::R
• pmu::hp_sleep_bias::SLEEP_R
• pmu::hp_sleep_bias::SLEEP_W
• pmu::hp_sleep_bias::W
• pmu::hp_sleep_dig_power::HP_SLEEP_HP_MEM_DSLP_R
• pmu::hp_sleep_dig_power::HP_SLEEP_HP_MEM_DSLP_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_AON_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_AON_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_CPU_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_CPU_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_MEM_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_MEM_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_WIFI_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_WIFI_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_TOP_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_TOP_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_VDD_SPI_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_VDD_SPI_PD_EN_W
• pmu::hp_sleep_dig_power::R
• pmu::hp_sleep_dig_power::W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_ISO_EN_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_ISO_EN_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_RETENTION_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_RETENTION_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_I2C_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_I2C_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BB_I2C_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BB_I2C_W
• pmu::hp_sleep_hp_ck_power::R
• pmu::hp_sleep_hp_ck_power::W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_XPD_W
• pmu::hp_sleep_hp_regulator0::R
• pmu::hp_sleep_hp_regulator0::W
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR_DRV_B_R
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR_DRV_B_W
• pmu::hp_sleep_hp_regulator1::R
• pmu::hp_sleep_hp_regulator1::W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_CPU_STALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_CPU_STALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAD_SLP_SEL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAD_SLP_SEL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAUSE_WDT_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAUSE_WDT_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_PAD_HOLD_ALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_PAD_HOLD_ALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_LP_PAD_HOLD_ALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_LP_PAD_HOLD_ALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_UART_WAKEUP_EN_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_UART_WAKEUP_EN_W
• pmu::hp_sleep_hp_sys_cntl::R
• pmu::hp_sleep_hp_sys_cntl::W
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_DIG_ICG_APB_EN_R
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_DIG_ICG_APB_EN_W
• pmu::hp_sleep_icg_hp_apb::R
• pmu::hp_sleep_icg_hp_apb::W
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_DIG_ICG_FUNC_EN_R
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_DIG_ICG_FUNC_EN_W
• pmu::hp_sleep_icg_hp_func::R
• pmu::hp_sleep_icg_hp_func::W
• pmu::hp_sleep_icg_modem::HP_SLEEP_DIG_ICG_MODEM_CODE_R
• pmu::hp_sleep_icg_modem::HP_SLEEP_DIG_ICG_MODEM_CODE_W
• pmu::hp_sleep_icg_modem::R
• pmu::hp_sleep_icg_modem::W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_PD_OSC_CLK_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_PD_OSC_CLK_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_FOSC_CLK_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_FOSC_CLK_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_RC32K_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_RC32K_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_XTAL32K_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_XTAL32K_W
• pmu::hp_sleep_lp_ck_power::R
• pmu::hp_sleep_lp_ck_power::W
• pmu::hp_sleep_lp_dcdc_reserve::HP_SLEEP_LP_DCDC_RESERVE_W
• pmu::hp_sleep_lp_dcdc_reserve::W
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_MEM_DSLP_R
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_MEM_DSLP_W
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_PD_LP_PERI_PD_EN_R
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_PD_LP_PERI_PD_EN_W
• pmu::hp_sleep_lp_dig_power::R
• pmu::hp_sleep_lp_dig_power::W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_DBIAS_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_DBIAS_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_DBIAS_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_DBIAS_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_XPD_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_XPD_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_XPD_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_XPD_W
• pmu::hp_sleep_lp_regulator0::R
• pmu::hp_sleep_lp_regulator0::W
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR_DRV_B_R
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR_DRV_B_W
• pmu::hp_sleep_lp_regulator1::R
• pmu::hp_sleep_lp_regulator1::W
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_SEL_W
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SLP_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SLP_SEL_W
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SYS_CLOCK_EN_R
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SYS_CLOCK_EN_W
• pmu::hp_sleep_sysclk::HP_SLEEP_SYS_CLK_SLP_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_SYS_CLK_SLP_SEL_W
• pmu::hp_sleep_sysclk::R
• pmu::hp_sleep_sysclk::W
• pmu::hp_sleep_xtal::HP_SLEEP_XPD_XTAL_R
• pmu::hp_sleep_xtal::HP_SLEEP_XPD_XTAL_W
• pmu::hp_sleep_xtal::R
• pmu::hp_sleep_xtal::W
• pmu::imm_hp_apb_icg::UPDATE_DIG_ICG_APB_EN_W
• pmu::imm_hp_apb_icg::W
• pmu::imm_hp_ck_power::R
• pmu::imm_hp_ck_power::TIE_HIGH_GLOBAL_BBPLL_ICG_W
• pmu::imm_hp_ck_power::TIE_HIGH_GLOBAL_XTAL_ICG_W
• pmu::imm_hp_ck_power::TIE_HIGH_I2C_RETENTION_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BBPLL_I2C_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BBPLL_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BB_I2C_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_XTAL_W
• pmu::imm_hp_ck_power::TIE_LOW_GLOBAL_BBPLL_ICG_W
• pmu::imm_hp_ck_power::TIE_LOW_GLOBAL_XTAL_ICG_W
• pmu::imm_hp_ck_power::TIE_LOW_I2C_RETENTION_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BBPLL_I2C_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BBPLL_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BB_I2C_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_XTAL_W
• pmu::imm_hp_ck_power::W
• pmu::imm_hp_func_icg::UPDATE_DIG_ICG_FUNC_EN_W
• pmu::imm_hp_func_icg::W
• pmu::imm_i2c_iso::TIE_HIGH_I2C_ISO_EN_W
• pmu::imm_i2c_iso::TIE_LOW_I2C_ISO_EN_W
• pmu::imm_i2c_iso::W
• pmu::imm_lp_icg::TIE_HIGH_LP_ROOTCLK_SEL_W
• pmu::imm_lp_icg::TIE_LOW_LP_ROOTCLK_SEL_W
• pmu::imm_lp_icg::W
• pmu::imm_modem_icg::UPDATE_DIG_ICG_MODEM_EN_W
• pmu::imm_modem_icg::W
• pmu::imm_pad_hold_all::TIE_HIGH_HP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_HIGH_LP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_LOW_HP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_LOW_LP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::W
• pmu::imm_sleep_sysclk::TIE_HIGH_ICG_SLP_SEL_W
• pmu::imm_sleep_sysclk::TIE_LOW_ICG_SLP_SEL_W
• pmu::imm_sleep_sysclk::UPDATE_DIG_ICG_SWITCH_W
• pmu::imm_sleep_sysclk::UPDATE_DIG_SYS_CLK_SEL_W
• pmu::imm_sleep_sysclk::W
• pmu::int_clr::LP_CPU_EXC_W
• pmu::int_clr::SDIO_IDLE_W
• pmu::int_clr::SOC_SLEEP_REJECT_W
• pmu::int_clr::SOC_WAKEUP_W
• pmu::int_clr::SW_W
• pmu::int_clr::W
• pmu::int_ena::LP_CPU_EXC_R
• pmu::int_ena::LP_CPU_EXC_W
• pmu::int_ena::R
• pmu::int_ena::SDIO_IDLE_R
• pmu::int_ena::SDIO_IDLE_W
• pmu::int_ena::SOC_SLEEP_REJECT_R
• pmu::int_ena::SOC_SLEEP_REJECT_W
• pmu::int_ena::SOC_WAKEUP_R
• pmu::int_ena::SOC_WAKEUP_W
• pmu::int_ena::SW_R
• pmu::int_ena::SW_W
• pmu::int_ena::W
• pmu::int_raw::LP_CPU_EXC_R
• pmu::int_raw::LP_CPU_EXC_W
• pmu::int_raw::R
• pmu::int_raw::SDIO_IDLE_R
• pmu::int_raw::SDIO_IDLE_W
• pmu::int_raw::SOC_SLEEP_REJECT_R
• pmu::int_raw::SOC_SLEEP_REJECT_W
• pmu::int_raw::SOC_WAKEUP_R
• pmu::int_raw::SOC_WAKEUP_W
• pmu::int_raw::SW_R
• pmu::int_raw::SW_W
• pmu::int_raw::W
• pmu::int_st::LP_CPU_EXC_R
• pmu::int_st::R
• pmu::int_st::SDIO_IDLE_R
• pmu::int_st::SOC_SLEEP_REJECT_R
• pmu::int_st::SOC_WAKEUP_R
• pmu::int_st::SW_R
• pmu::lp_cpu_pwr0::LP_CPU_FORCE_STALL_R
• pmu::lp_cpu_pwr0::LP_CPU_FORCE_STALL_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_BYPASS_INTR_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_BYPASS_INTR_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_RESET_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_RESET_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_FLAG_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_FLAG_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_WAIT_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_WAIT_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_WAITI_FLAG_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_WAITI_FLAG_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_STALL_RDY_R
• pmu::lp_cpu_pwr0::LP_CPU_WAITI_RDY_R
• pmu::lp_cpu_pwr0::R
• pmu::lp_cpu_pwr0::W
• pmu::lp_cpu_pwr1::LP_CPU_SLEEP_REQ_W
• pmu::lp_cpu_pwr1::LP_CPU_WAKEUP_EN_R
• pmu::lp_cpu_pwr1::LP_CPU_WAKEUP_EN_W
• pmu::lp_cpu_pwr1::R
• pmu::lp_cpu_pwr1::W
• pmu::lp_int_clr::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_clr::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_clr::HP_SW_TRIGGER_W
• pmu::lp_int_clr::LP_CPU_WAKEUP_W
• pmu::lp_int_clr::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_clr::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_clr::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_clr::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_clr::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_clr::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_clr::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_clr::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_clr::W
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_ena::HP_SW_TRIGGER_R
• pmu::lp_int_ena::HP_SW_TRIGGER_W
• pmu::lp_int_ena::LP_CPU_WAKEUP_R
• pmu::lp_int_ena::LP_CPU_WAKEUP_W
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_ena::R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_ena::W
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_raw::HP_SW_TRIGGER_R
• pmu::lp_int_raw::HP_SW_TRIGGER_W
• pmu::lp_int_raw::LP_CPU_WAKEUP_R
• pmu::lp_int_raw::LP_CPU_WAKEUP_W
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_raw::R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_raw::W
• pmu::lp_int_st::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_st::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_st::HP_SW_TRIGGER_R
• pmu::lp_int_st::LP_CPU_WAKEUP_R
• pmu::lp_int_st::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_st::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_st::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_st::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_st::R
• pmu::lp_int_st::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_st::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_st::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_st::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_sleep_bias::LP_SLEEP_DBG_ATTEN_R
• pmu::lp_sleep_bias::LP_SLEEP_DBG_ATTEN_W
• pmu::lp_sleep_bias::LP_SLEEP_PD_CUR_R
• pmu::lp_sleep_bias::LP_SLEEP_PD_CUR_W
• pmu::lp_sleep_bias::LP_SLEEP_XPD_BIAS_R
• pmu::lp_sleep_bias::LP_SLEEP_XPD_BIAS_W
• pmu::lp_sleep_bias::R
• pmu::lp_sleep_bias::SLEEP_R
• pmu::lp_sleep_bias::SLEEP_W
• pmu::lp_sleep_bias::W
• pmu::lp_sleep_lp_bias_reserve::LP_SLEEP_LP_BIAS_RESERVE_W
• pmu::lp_sleep_lp_bias_reserve::W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_PD_OSC_CLK_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_PD_OSC_CLK_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_FOSC_CLK_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_FOSC_CLK_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_RC32K_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_RC32K_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_XTAL32K_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_XTAL32K_W
• pmu::lp_sleep_lp_ck_power::R
• pmu::lp_sleep_lp_ck_power::W
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_MEM_DSLP_R
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_MEM_DSLP_W
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_PD_LP_PERI_PD_EN_R
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_PD_LP_PERI_PD_EN_W
• pmu::lp_sleep_lp_dig_power::R
• pmu::lp_sleep_lp_dig_power::W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_DBIAS_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_DBIAS_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_DBIAS_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_DBIAS_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_XPD_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_XPD_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_XPD_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_XPD_W
• pmu::lp_sleep_lp_regulator0::R
• pmu::lp_sleep_lp_regulator0::W
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR_DRV_B_R
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR_DRV_B_W
• pmu::lp_sleep_lp_regulator1::R
• pmu::lp_sleep_lp_regulator1::W
• pmu::lp_sleep_xtal::LP_SLEEP_XPD_XTAL_R
• pmu::lp_sleep_xtal::LP_SLEEP_XPD_XTAL_W
• pmu::lp_sleep_xtal::R
• pmu::lp_sleep_xtal::W
• pmu::main_state::MAIN_CUR_ST_STATE_R
• pmu::main_state::MAIN_LAST_ST_STATE_R
• pmu::main_state::MAIN_TAR_ST_STATE_R
• pmu::main_state::R
• pmu::por_status::POR_DONE_R
• pmu::por_status::R
• pmu::power_ck_wait_cntl::R
• pmu::power_ck_wait_cntl::W
• pmu::power_ck_wait_cntl::WAIT_PLL_STABLE_R
• pmu::power_ck_wait_cntl::WAIT_PLL_STABLE_W
• pmu::power_ck_wait_cntl::WAIT_XTL_STABLE_R
• pmu::power_ck_wait_cntl::WAIT_XTL_STABLE_W
• pmu::power_hp_pad::FORCE_HP_PAD_ISO_ALL_R
• pmu::power_hp_pad::FORCE_HP_PAD_ISO_ALL_W
• pmu::power_hp_pad::FORCE_HP_PAD_NO_ISO_ALL_R
• pmu::power_hp_pad::FORCE_HP_PAD_NO_ISO_ALL_W
• pmu::power_hp_pad::R
• pmu::power_hp_pad::W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_ISO_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_ISO_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_ISO_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_ISO_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_RESET_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_RESET_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PD_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PD_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PU_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PU_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_RESET_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_RESET_W
• pmu::power_pd_hpaon_cntl::PD_HP_AON_MASK_R
• pmu::power_pd_hpaon_cntl::PD_HP_AON_MASK_W
• pmu::power_pd_hpaon_cntl::PD_HP_AON_PD_MASK_R
• pmu::power_pd_hpaon_cntl::PD_HP_AON_PD_MASK_W
• pmu::power_pd_hpaon_cntl::R
• pmu::power_pd_hpaon_cntl::W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_ISO_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_ISO_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_ISO_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_ISO_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_RESET_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_RESET_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PD_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PD_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PU_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PU_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_RESET_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_RESET_W
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_MASK_R
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_MASK_W
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_PD_MASK_R
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_PD_MASK_W
• pmu::power_pd_hpcpu_cntl::R
• pmu::power_pd_hpcpu_cntl::W
• pmu::power_pd_hpperi_reserve::HP_PERI_RESERVE_W
• pmu::power_pd_hpperi_reserve::W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_ISO_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_ISO_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_ISO_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_ISO_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_RESET_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_RESET_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PD_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PD_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PU_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PU_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_RESET_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_RESET_W
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_MASK_R
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_MASK_W
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_PD_MASK_R
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_PD_MASK_W
• pmu::power_pd_hpwifi_cntl::R
• pmu::power_pd_hpwifi_cntl::W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_ISO_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_ISO_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_ISO_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_ISO_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_RESET_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_RESET_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PD_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PD_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PU_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PU_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_RESET_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_RESET_W
• pmu::power_pd_lpperi_cntl::R
• pmu::power_pd_lpperi_cntl::W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_ISO_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_ISO_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_NO_ISO_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_NO_ISO_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PD_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PD_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PU_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PU_W
• pmu::power_pd_mem_cntl::R
• pmu::power_pd_mem_cntl::W
• pmu::power_pd_mem_mask::PD_HP_MEM0_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM0_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM0_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM0_PD_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM1_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM1_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM1_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM1_PD_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM2_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM2_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM2_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM2_PD_MASK_W
• pmu::power_pd_mem_mask::R
• pmu::power_pd_mem_mask::W
• pmu::power_pd_top_cntl::FORCE_TOP_ISO_R
• pmu::power_pd_top_cntl::FORCE_TOP_ISO_W
• pmu::power_pd_top_cntl::FORCE_TOP_NO_ISO_R
• pmu::power_pd_top_cntl::FORCE_TOP_NO_ISO_W
• pmu::power_pd_top_cntl::FORCE_TOP_NO_RESET_R
• pmu::power_pd_top_cntl::FORCE_TOP_NO_RESET_W
• pmu::power_pd_top_cntl::FORCE_TOP_PD_R
• pmu::power_pd_top_cntl::FORCE_TOP_PD_W
• pmu::power_pd_top_cntl::FORCE_TOP_PU_R
• pmu::power_pd_top_cntl::FORCE_TOP_PU_W
• pmu::power_pd_top_cntl::FORCE_TOP_RESET_R
• pmu::power_pd_top_cntl::FORCE_TOP_RESET_W
• pmu::power_pd_top_cntl::PD_TOP_MASK_R
• pmu::power_pd_top_cntl::PD_TOP_MASK_W
• pmu::power_pd_top_cntl::PD_TOP_PD_MASK_R
• pmu::power_pd_top_cntl::PD_TOP_PD_MASK_W
• pmu::power_pd_top_cntl::R
• pmu::power_pd_top_cntl::W
• pmu::power_vdd_spi_cntl::R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SEL_SW_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SEL_SW_W
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SW_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SW_W
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_WAIT_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_WAIT_W
• pmu::power_vdd_spi_cntl::W
• pmu::power_wait_timer0::DG_HP_POWERDOWN_TIMER_R
• pmu::power_wait_timer0::DG_HP_POWERDOWN_TIMER_W
• pmu::power_wait_timer0::DG_HP_POWERUP_TIMER_R
• pmu::power_wait_timer0::DG_HP_POWERUP_TIMER_W
• pmu::power_wait_timer0::DG_HP_WAIT_TIMER_R
• pmu::power_wait_timer0::DG_HP_WAIT_TIMER_W
• pmu::power_wait_timer0::R
• pmu::power_wait_timer0::W
• pmu::power_wait_timer1::DG_LP_POWERDOWN_TIMER_R
• pmu::power_wait_timer1::DG_LP_POWERDOWN_TIMER_W
• pmu::power_wait_timer1::DG_LP_POWERUP_TIMER_R
• pmu::power_wait_timer1::DG_LP_POWERUP_TIMER_W
• pmu::power_wait_timer1::DG_LP_WAIT_TIMER_R
• pmu::power_wait_timer1::DG_LP_WAIT_TIMER_W
• pmu::power_wait_timer1::R
• pmu::power_wait_timer1::W
• pmu::pwr_state::BACKUP_ST_STATE_R
• pmu::pwr_state::HP_PWR_ST_STATE_R
• pmu::pwr_state::LP_PWR_ST_STATE_R
• pmu::pwr_state::R
• pmu::rf_pwc::PERIF_I2C_RSTB_R
• pmu::rf_pwc::PERIF_I2C_RSTB_W
• pmu::rf_pwc::R
• pmu::rf_pwc::W
• pmu::rf_pwc::XPD_CKGEN_I2C_R
• pmu::rf_pwc::XPD_CKGEN_I2C_W
• pmu::rf_pwc::XPD_PERIF_I2C_R
• pmu::rf_pwc::XPD_PERIF_I2C_W
• pmu::rf_pwc::XPD_PLL_I2C_R
• pmu::rf_pwc::XPD_PLL_I2C_W
• pmu::rf_pwc::XPD_RFRX_PBUS_R
• pmu::rf_pwc::XPD_RFRX_PBUS_W
• pmu::rf_pwc::XPD_TXRF_I2C_R
• pmu::rf_pwc::XPD_TXRF_I2C_W
• pmu::slp_wakeup_cntl0::SLEEP_REQ_W
• pmu::slp_wakeup_cntl0::W
• pmu::slp_wakeup_cntl1::R
• pmu::slp_wakeup_cntl1::SLEEP_REJECT_ENA_R
• pmu::slp_wakeup_cntl1::SLEEP_REJECT_ENA_W
• pmu::slp_wakeup_cntl1::SLP_REJECT_EN_R
• pmu::slp_wakeup_cntl1::SLP_REJECT_EN_W
• pmu::slp_wakeup_cntl1::W
• pmu::slp_wakeup_cntl2::R
• pmu::slp_wakeup_cntl2::W
• pmu::slp_wakeup_cntl2::WAKEUP_ENA_R
• pmu::slp_wakeup_cntl2::WAKEUP_ENA_W
• pmu::slp_wakeup_cntl3::HP_MIN_SLP_VAL_R
• pmu::slp_wakeup_cntl3::HP_MIN_SLP_VAL_W
• pmu::slp_wakeup_cntl3::LP_MIN_SLP_VAL_R
• pmu::slp_wakeup_cntl3::LP_MIN_SLP_VAL_W
• pmu::slp_wakeup_cntl3::R
• pmu::slp_wakeup_cntl3::SLEEP_PRT_SEL_R
• pmu::slp_wakeup_cntl3::SLEEP_PRT_SEL_W
• pmu::slp_wakeup_cntl3::W
• pmu::slp_wakeup_cntl4::SLP_REJECT_CAUSE_CLR_W
• pmu::slp_wakeup_cntl4::W
• pmu::slp_wakeup_cntl5::LP_ANA_WAIT_TARGET_R
• pmu::slp_wakeup_cntl5::LP_ANA_WAIT_TARGET_W
• pmu::slp_wakeup_cntl5::MODEM_WAIT_TARGET_R
• pmu::slp_wakeup_cntl5::MODEM_WAIT_TARGET_W
• pmu::slp_wakeup_cntl5::R
• pmu::slp_wakeup_cntl5::W
• pmu::slp_wakeup_cntl6::R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_CFG_R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_CFG_W
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_W
• pmu::slp_wakeup_cntl6::W
• pmu::slp_wakeup_cntl7::ANA_WAIT_TARGET_R
• pmu::slp_wakeup_cntl7::ANA_WAIT_TARGET_W
• pmu::slp_wakeup_cntl7::R
• pmu::slp_wakeup_cntl7::W
• pmu::slp_wakeup_status0::R
• pmu::slp_wakeup_status0::WAKEUP_CAUSE_R
• pmu::slp_wakeup_status1::R
• pmu::slp_wakeup_status1::REJECT_CAUSE_R
• pmu::vdd_spi_status::R
• pmu::vdd_spi_status::STABLE_VDD_SPI_PWR_DRV_R

Constants

• NVIC_PRIO_BITS