esp32c6_lp/lp_uart/
int_st.rs1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `RXFIFO_FULL` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
4pub type RXFIFO_FULL_R = crate::BitReader;
5#[doc = "Field `TXFIFO_EMPTY` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
6pub type TXFIFO_EMPTY_R = crate::BitReader;
7#[doc = "Field `PARITY_ERR` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
8pub type PARITY_ERR_R = crate::BitReader;
9#[doc = "Field `FRM_ERR` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
10pub type FRM_ERR_R = crate::BitReader;
11#[doc = "Field `RXFIFO_OVF` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
12pub type RXFIFO_OVF_R = crate::BitReader;
13#[doc = "Field `DSR_CHG` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
14pub type DSR_CHG_R = crate::BitReader;
15#[doc = "Field `CTS_CHG` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
16pub type CTS_CHG_R = crate::BitReader;
17#[doc = "Field `BRK_DET` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
18pub type BRK_DET_R = crate::BitReader;
19#[doc = "Field `RXFIFO_TOUT` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
20pub type RXFIFO_TOUT_R = crate::BitReader;
21#[doc = "Field `SW_XON` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
22pub type SW_XON_R = crate::BitReader;
23#[doc = "Field `SW_XOFF` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
24pub type SW_XOFF_R = crate::BitReader;
25#[doc = "Field `GLITCH_DET` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
26pub type GLITCH_DET_R = crate::BitReader;
27#[doc = "Field `TX_BRK_DONE` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
28pub type TX_BRK_DONE_R = crate::BitReader;
29#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
30pub type TX_BRK_IDLE_DONE_R = crate::BitReader;
31#[doc = "Field `TX_DONE` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
32pub type TX_DONE_R = crate::BitReader;
33#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
34pub type AT_CMD_CHAR_DET_R = crate::BitReader;
35#[doc = "Field `WAKEUP` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
36pub type WAKEUP_R = crate::BitReader;
37impl R {
38 #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
39 #[inline(always)]
40 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
41 RXFIFO_FULL_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
44 #[inline(always)]
45 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
46 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
49 #[inline(always)]
50 pub fn parity_err(&self) -> PARITY_ERR_R {
51 PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
54 #[inline(always)]
55 pub fn frm_err(&self) -> FRM_ERR_R {
56 FRM_ERR_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
59 #[inline(always)]
60 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
61 RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
64 #[inline(always)]
65 pub fn dsr_chg(&self) -> DSR_CHG_R {
66 DSR_CHG_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
69 #[inline(always)]
70 pub fn cts_chg(&self) -> CTS_CHG_R {
71 CTS_CHG_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
74 #[inline(always)]
75 pub fn brk_det(&self) -> BRK_DET_R {
76 BRK_DET_R::new(((self.bits >> 7) & 1) != 0)
77 }
78 #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
79 #[inline(always)]
80 pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R {
81 RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0)
82 }
83 #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
84 #[inline(always)]
85 pub fn sw_xon(&self) -> SW_XON_R {
86 SW_XON_R::new(((self.bits >> 9) & 1) != 0)
87 }
88 #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
89 #[inline(always)]
90 pub fn sw_xoff(&self) -> SW_XOFF_R {
91 SW_XOFF_R::new(((self.bits >> 10) & 1) != 0)
92 }
93 #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
94 #[inline(always)]
95 pub fn glitch_det(&self) -> GLITCH_DET_R {
96 GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0)
97 }
98 #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
99 #[inline(always)]
100 pub fn tx_brk_done(&self) -> TX_BRK_DONE_R {
101 TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0)
102 }
103 #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
104 #[inline(always)]
105 pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R {
106 TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0)
107 }
108 #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
109 #[inline(always)]
110 pub fn tx_done(&self) -> TX_DONE_R {
111 TX_DONE_R::new(((self.bits >> 14) & 1) != 0)
112 }
113 #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
114 #[inline(always)]
115 pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R {
116 AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0)
117 }
118 #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
119 #[inline(always)]
120 pub fn wakeup(&self) -> WAKEUP_R {
121 WAKEUP_R::new(((self.bits >> 19) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("INT_ST")
128 .field("rxfifo_full", &self.rxfifo_full())
129 .field("txfifo_empty", &self.txfifo_empty())
130 .field("parity_err", &self.parity_err())
131 .field("frm_err", &self.frm_err())
132 .field("rxfifo_ovf", &self.rxfifo_ovf())
133 .field("dsr_chg", &self.dsr_chg())
134 .field("cts_chg", &self.cts_chg())
135 .field("brk_det", &self.brk_det())
136 .field("rxfifo_tout", &self.rxfifo_tout())
137 .field("sw_xon", &self.sw_xon())
138 .field("sw_xoff", &self.sw_xoff())
139 .field("glitch_det", &self.glitch_det())
140 .field("tx_brk_done", &self.tx_brk_done())
141 .field("tx_brk_idle_done", &self.tx_brk_idle_done())
142 .field("tx_done", &self.tx_done())
143 .field("at_cmd_char_det", &self.at_cmd_char_det())
144 .field("wakeup", &self.wakeup())
145 .finish()
146 }
147}
148#[doc = "Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
149pub struct INT_ST_SPEC;
150impl crate::RegisterSpec for INT_ST_SPEC {
151 type Ux = u32;
152}
153#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
154impl crate::Readable for INT_ST_SPEC {}
155#[doc = "`reset()` method sets INT_ST to value 0"]
156impl crate::Resettable for INT_ST_SPEC {
157 const RESET_VALUE: u32 = 0;
158}