esp32c6_lp/lp_uart/
clkdiv_sync.rs

1#[doc = "Register `CLKDIV_SYNC` reader"]
2pub type R = crate::R<CLKDIV_SYNC_SPEC>;
3#[doc = "Register `CLKDIV_SYNC` writer"]
4pub type W = crate::W<CLKDIV_SYNC_SPEC>;
5#[doc = "Field `CLKDIV` reader - The integral part of the frequency divider factor."]
6pub type CLKDIV_R = crate::FieldReader<u16>;
7#[doc = "Field `CLKDIV` writer - The integral part of the frequency divider factor."]
8pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `CLKDIV_FRAG` reader - The decimal part of the frequency divider factor."]
10pub type CLKDIV_FRAG_R = crate::FieldReader;
11#[doc = "Field `CLKDIV_FRAG` writer - The decimal part of the frequency divider factor."]
12pub type CLKDIV_FRAG_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
15    #[inline(always)]
16    pub fn clkdiv(&self) -> CLKDIV_R {
17        CLKDIV_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
20    #[inline(always)]
21    pub fn clkdiv_frag(&self) -> CLKDIV_FRAG_R {
22        CLKDIV_FRAG_R::new(((self.bits >> 20) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CLKDIV_SYNC")
29            .field("clkdiv", &self.clkdiv())
30            .field("clkdiv_frag", &self.clkdiv_frag())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:11 - The integral part of the frequency divider factor."]
36    #[inline(always)]
37    #[must_use]
38    pub fn clkdiv(&mut self) -> CLKDIV_W<CLKDIV_SYNC_SPEC> {
39        CLKDIV_W::new(self, 0)
40    }
41    #[doc = "Bits 20:23 - The decimal part of the frequency divider factor."]
42    #[inline(always)]
43    #[must_use]
44    pub fn clkdiv_frag(&mut self) -> CLKDIV_FRAG_W<CLKDIV_SYNC_SPEC> {
45        CLKDIV_FRAG_W::new(self, 20)
46    }
47}
48#[doc = "Clock divider configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv_sync::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv_sync::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
49pub struct CLKDIV_SYNC_SPEC;
50impl crate::RegisterSpec for CLKDIV_SYNC_SPEC {
51    type Ux = u32;
52}
53#[doc = "`read()` method returns [`clkdiv_sync::R`](R) reader structure"]
54impl crate::Readable for CLKDIV_SYNC_SPEC {}
55#[doc = "`write(|w| ..)` method takes [`clkdiv_sync::W`](W) writer structure"]
56impl crate::Writable for CLKDIV_SYNC_SPEC {
57    type Safety = crate::Unsafe;
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
60}
61#[doc = "`reset()` method sets CLKDIV_SYNC to value 0x02b6"]
62impl crate::Resettable for CLKDIV_SYNC_SPEC {
63    const RESET_VALUE: u32 = 0x02b6;
64}
esp32c6_lp/lp_uart/clkdiv_sync.rs

esp32c6_lp/lp_uart/
clkdiv_sync.rs
