esp32c6_lp/lp_aon/
cpucore0_cfg.rs

1#[doc = "Register `CPUCORE0_CFG` reader"]
2pub type R = crate::R<CPUCORE0_CFG_SPEC>;
3#[doc = "Register `CPUCORE0_CFG` writer"]
4pub type W = crate::W<CPUCORE0_CFG_SPEC>;
5#[doc = "Field `CPU_CORE0_SW_STALL` reader - need_des"]
6pub type CPU_CORE0_SW_STALL_R = crate::FieldReader;
7#[doc = "Field `CPU_CORE0_SW_STALL` writer - need_des"]
8pub type CPU_CORE0_SW_STALL_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `CPU_CORE0_SW_RESET` writer - need_des"]
10pub type CPU_CORE0_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CPU_CORE0_OCD_HALT_ON_RESET` reader - need_des"]
12pub type CPU_CORE0_OCD_HALT_ON_RESET_R = crate::BitReader;
13#[doc = "Field `CPU_CORE0_OCD_HALT_ON_RESET` writer - need_des"]
14pub type CPU_CORE0_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `CPU_CORE0_STAT_VECTOR_SEL` reader - need_des"]
16pub type CPU_CORE0_STAT_VECTOR_SEL_R = crate::BitReader;
17#[doc = "Field `CPU_CORE0_STAT_VECTOR_SEL` writer - need_des"]
18pub type CPU_CORE0_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `CPU_CORE0_DRESET_MASK` reader - need_des"]
20pub type CPU_CORE0_DRESET_MASK_R = crate::BitReader;
21#[doc = "Field `CPU_CORE0_DRESET_MASK` writer - need_des"]
22pub type CPU_CORE0_DRESET_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
23impl R {
24    #[doc = "Bits 0:7 - need_des"]
25    #[inline(always)]
26    pub fn cpu_core0_sw_stall(&self) -> CPU_CORE0_SW_STALL_R {
27        CPU_CORE0_SW_STALL_R::new((self.bits & 0xff) as u8)
28    }
29    #[doc = "Bit 29 - need_des"]
30    #[inline(always)]
31    pub fn cpu_core0_ocd_halt_on_reset(&self) -> CPU_CORE0_OCD_HALT_ON_RESET_R {
32        CPU_CORE0_OCD_HALT_ON_RESET_R::new(((self.bits >> 29) & 1) != 0)
33    }
34    #[doc = "Bit 30 - need_des"]
35    #[inline(always)]
36    pub fn cpu_core0_stat_vector_sel(&self) -> CPU_CORE0_STAT_VECTOR_SEL_R {
37        CPU_CORE0_STAT_VECTOR_SEL_R::new(((self.bits >> 30) & 1) != 0)
38    }
39    #[doc = "Bit 31 - need_des"]
40    #[inline(always)]
41    pub fn cpu_core0_dreset_mask(&self) -> CPU_CORE0_DRESET_MASK_R {
42        CPU_CORE0_DRESET_MASK_R::new(((self.bits >> 31) & 1) != 0)
43    }
44}
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for R {
47    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
48        f.debug_struct("CPUCORE0_CFG")
49            .field("cpu_core0_sw_stall", &self.cpu_core0_sw_stall())
50            .field(
51                "cpu_core0_ocd_halt_on_reset",
52                &self.cpu_core0_ocd_halt_on_reset(),
53            )
54            .field(
55                "cpu_core0_stat_vector_sel",
56                &self.cpu_core0_stat_vector_sel(),
57            )
58            .field("cpu_core0_dreset_mask", &self.cpu_core0_dreset_mask())
59            .finish()
60    }
61}
62impl W {
63    #[doc = "Bits 0:7 - need_des"]
64    #[inline(always)]
65    #[must_use]
66    pub fn cpu_core0_sw_stall(&mut self) -> CPU_CORE0_SW_STALL_W<CPUCORE0_CFG_SPEC> {
67        CPU_CORE0_SW_STALL_W::new(self, 0)
68    }
69    #[doc = "Bit 28 - need_des"]
70    #[inline(always)]
71    #[must_use]
72    pub fn cpu_core0_sw_reset(&mut self) -> CPU_CORE0_SW_RESET_W<CPUCORE0_CFG_SPEC> {
73        CPU_CORE0_SW_RESET_W::new(self, 28)
74    }
75    #[doc = "Bit 29 - need_des"]
76    #[inline(always)]
77    #[must_use]
78    pub fn cpu_core0_ocd_halt_on_reset(
79        &mut self,
80    ) -> CPU_CORE0_OCD_HALT_ON_RESET_W<CPUCORE0_CFG_SPEC> {
81        CPU_CORE0_OCD_HALT_ON_RESET_W::new(self, 29)
82    }
83    #[doc = "Bit 30 - need_des"]
84    #[inline(always)]
85    #[must_use]
86    pub fn cpu_core0_stat_vector_sel(&mut self) -> CPU_CORE0_STAT_VECTOR_SEL_W<CPUCORE0_CFG_SPEC> {
87        CPU_CORE0_STAT_VECTOR_SEL_W::new(self, 30)
88    }
89    #[doc = "Bit 31 - need_des"]
90    #[inline(always)]
91    #[must_use]
92    pub fn cpu_core0_dreset_mask(&mut self) -> CPU_CORE0_DRESET_MASK_W<CPUCORE0_CFG_SPEC> {
93        CPU_CORE0_DRESET_MASK_W::new(self, 31)
94    }
95}
96#[doc = "need_des\n\nYou can [`read`](crate::Reg::read) this register and get [`cpucore0_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cpucore0_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct CPUCORE0_CFG_SPEC;
98impl crate::RegisterSpec for CPUCORE0_CFG_SPEC {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`cpucore0_cfg::R`](R) reader structure"]
102impl crate::Readable for CPUCORE0_CFG_SPEC {}
103#[doc = "`write(|w| ..)` method takes [`cpucore0_cfg::W`](W) writer structure"]
104impl crate::Writable for CPUCORE0_CFG_SPEC {
105    type Safety = crate::Unsafe;
106    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
108}
109#[doc = "`reset()` method sets CPUCORE0_CFG to value 0x4000_0000"]
110impl crate::Resettable for CPUCORE0_CFG_SPEC {
111    const RESET_VALUE: u32 = 0x4000_0000;
112}
esp32c6_lp/lp_aon/cpucore0_cfg.rs

esp32c6_lp/lp_aon/
cpucore0_cfg.rs
