1#[doc = "Register `DMA_CONF` reader"]
2pub type R = crate::R<DMA_CONF_SPEC>;
3#[doc = "Register `DMA_CONF` writer"]
4pub type W = crate::W<DMA_CONF_SPEC>;
5#[doc = "Field `DMA_SLV_SEG_TRANS_EN` reader - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
6pub type DMA_SLV_SEG_TRANS_EN_R = crate::BitReader;
7#[doc = "Field `DMA_SLV_SEG_TRANS_EN` writer - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
8pub type DMA_SLV_SEG_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SLV_RX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
10pub type SLV_RX_SEG_TRANS_CLR_EN_R = crate::BitReader;
11#[doc = "Field `SLV_RX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
12pub type SLV_RX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SLV_TX_SEG_TRANS_CLR_EN` reader - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
14pub type SLV_TX_SEG_TRANS_CLR_EN_R = crate::BitReader;
15#[doc = "Field `SLV_TX_SEG_TRANS_CLR_EN` writer - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
16pub type SLV_TX_SEG_TRANS_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_EOF_EN` reader - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
18pub type RX_EOF_EN_R = crate::BitReader;
19#[doc = "Field `RX_EOF_EN` writer - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
20pub type RX_EOF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DMA_RX_ENA` reader - Set this bit to enable SPI DMA controlled receive data mode."]
22pub type DMA_RX_ENA_R = crate::BitReader;
23#[doc = "Field `DMA_RX_ENA` writer - Set this bit to enable SPI DMA controlled receive data mode."]
24pub type DMA_RX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DMA_TX_ENA` reader - Set this bit to enable SPI DMA controlled send data mode."]
26pub type DMA_TX_ENA_R = crate::BitReader;
27#[doc = "Field `DMA_TX_ENA` writer - Set this bit to enable SPI DMA controlled send data mode."]
28pub type DMA_TX_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `RX_AFIFO_RST` writer - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."]
30pub type RX_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `BUF_AFIFO_RST` writer - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."]
32pub type BUF_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DMA_AFIFO_RST` writer - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."]
34pub type DMA_AFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
35impl R {
36 #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
37 #[inline(always)]
38 pub fn dma_slv_seg_trans_en(&self) -> DMA_SLV_SEG_TRANS_EN_R {
39 DMA_SLV_SEG_TRANS_EN_R::new(((self.bits >> 18) & 1) != 0)
40 }
41 #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
42 #[inline(always)]
43 pub fn slv_rx_seg_trans_clr_en(&self) -> SLV_RX_SEG_TRANS_CLR_EN_R {
44 SLV_RX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 19) & 1) != 0)
45 }
46 #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
47 #[inline(always)]
48 pub fn slv_tx_seg_trans_clr_en(&self) -> SLV_TX_SEG_TRANS_CLR_EN_R {
49 SLV_TX_SEG_TRANS_CLR_EN_R::new(((self.bits >> 20) & 1) != 0)
50 }
51 #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
52 #[inline(always)]
53 pub fn rx_eof_en(&self) -> RX_EOF_EN_R {
54 RX_EOF_EN_R::new(((self.bits >> 21) & 1) != 0)
55 }
56 #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."]
57 #[inline(always)]
58 pub fn dma_rx_ena(&self) -> DMA_RX_ENA_R {
59 DMA_RX_ENA_R::new(((self.bits >> 27) & 1) != 0)
60 }
61 #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."]
62 #[inline(always)]
63 pub fn dma_tx_ena(&self) -> DMA_TX_ENA_R {
64 DMA_TX_ENA_R::new(((self.bits >> 28) & 1) != 0)
65 }
66}
67#[cfg(feature = "impl-register-debug")]
68impl core::fmt::Debug for R {
69 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
70 f.debug_struct("DMA_CONF")
71 .field("dma_slv_seg_trans_en", &self.dma_slv_seg_trans_en())
72 .field("slv_rx_seg_trans_clr_en", &self.slv_rx_seg_trans_clr_en())
73 .field("slv_tx_seg_trans_clr_en", &self.slv_tx_seg_trans_clr_en())
74 .field("rx_eof_en", &self.rx_eof_en())
75 .field("dma_rx_ena", &self.dma_rx_ena())
76 .field("dma_tx_ena", &self.dma_tx_ena())
77 .finish()
78 }
79}
80impl W {
81 #[doc = "Bit 18 - Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable."]
82 #[inline(always)]
83 pub fn dma_slv_seg_trans_en(&mut self) -> DMA_SLV_SEG_TRANS_EN_W<DMA_CONF_SPEC> {
84 DMA_SLV_SEG_TRANS_EN_W::new(self, 18)
85 }
86 #[doc = "Bit 19 - 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done."]
87 #[inline(always)]
88 pub fn slv_rx_seg_trans_clr_en(&mut self) -> SLV_RX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
89 SLV_RX_SEG_TRANS_CLR_EN_W::new(self, 19)
90 }
91 #[doc = "Bit 20 - 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done."]
92 #[inline(always)]
93 pub fn slv_tx_seg_trans_clr_en(&mut self) -> SLV_TX_SEG_TRANS_CLR_EN_W<DMA_CONF_SPEC> {
94 SLV_TX_SEG_TRANS_CLR_EN_W::new(self, 20)
95 }
96 #[doc = "Bit 21 - 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen\\[19:0\\] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans."]
97 #[inline(always)]
98 pub fn rx_eof_en(&mut self) -> RX_EOF_EN_W<DMA_CONF_SPEC> {
99 RX_EOF_EN_W::new(self, 21)
100 }
101 #[doc = "Bit 27 - Set this bit to enable SPI DMA controlled receive data mode."]
102 #[inline(always)]
103 pub fn dma_rx_ena(&mut self) -> DMA_RX_ENA_W<DMA_CONF_SPEC> {
104 DMA_RX_ENA_W::new(self, 27)
105 }
106 #[doc = "Bit 28 - Set this bit to enable SPI DMA controlled send data mode."]
107 #[inline(always)]
108 pub fn dma_tx_ena(&mut self) -> DMA_TX_ENA_W<DMA_CONF_SPEC> {
109 DMA_TX_ENA_W::new(self, 28)
110 }
111 #[doc = "Bit 29 - Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer."]
112 #[inline(always)]
113 pub fn rx_afifo_rst(&mut self) -> RX_AFIFO_RST_W<DMA_CONF_SPEC> {
114 RX_AFIFO_RST_W::new(self, 29)
115 }
116 #[doc = "Bit 30 - Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer."]
117 #[inline(always)]
118 pub fn buf_afifo_rst(&mut self) -> BUF_AFIFO_RST_W<DMA_CONF_SPEC> {
119 BUF_AFIFO_RST_W::new(self, 30)
120 }
121 #[doc = "Bit 31 - Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer."]
122 #[inline(always)]
123 pub fn dma_afifo_rst(&mut self) -> DMA_AFIFO_RST_W<DMA_CONF_SPEC> {
124 DMA_AFIFO_RST_W::new(self, 31)
125 }
126}
127#[doc = "SPI DMA control register\n\nYou can [`read`](crate::Reg::read) this register and get [`dma_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dma_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
128pub struct DMA_CONF_SPEC;
129impl crate::RegisterSpec for DMA_CONF_SPEC {
130 type Ux = u32;
131}
132#[doc = "`read()` method returns [`dma_conf::R`](R) reader structure"]
133impl crate::Readable for DMA_CONF_SPEC {}
134#[doc = "`write(|w| ..)` method takes [`dma_conf::W`](W) writer structure"]
135impl crate::Writable for DMA_CONF_SPEC {
136 type Safety = crate::Unsafe;
137 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
138 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
139}
140#[doc = "`reset()` method sets DMA_CONF to value 0"]
141impl crate::Resettable for DMA_CONF_SPEC {
142 const RESET_VALUE: u32 = 0;
143}