esp32c3/spi0/
core_clk_sel.rs

1#[doc = "Register `CORE_CLK_SEL` reader"]
2pub type R = crate::R<CORE_CLK_SEL_SPEC>;
3#[doc = "Register `CORE_CLK_SEL` writer"]
4pub type W = crate::W<CORE_CLK_SEL_SPEC>;
5#[doc = "Field `SPI01_CLK_SEL` reader - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
6pub type SPI01_CLK_SEL_R = crate::FieldReader;
7#[doc = "Field `SPI01_CLK_SEL` writer - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
8pub type SPI01_CLK_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9impl R {
10    #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
11    #[inline(always)]
12    pub fn spi01_clk_sel(&self) -> SPI01_CLK_SEL_R {
13        SPI01_CLK_SEL_R::new((self.bits & 3) as u8)
14    }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("CORE_CLK_SEL")
20            .field("spi01_clk_sel", &self.spi01_clk_sel())
21            .finish()
22    }
23}
24impl W {
25    #[doc = "Bits 0:1 - When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used."]
26    #[inline(always)]
27    pub fn spi01_clk_sel(&mut self) -> SPI01_CLK_SEL_W<CORE_CLK_SEL_SPEC> {
28        SPI01_CLK_SEL_W::new(self, 0)
29    }
30}
31#[doc = "SPI0 module clock select register\n\nYou can [`read`](crate::Reg::read) this register and get [`core_clk_sel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_clk_sel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
32pub struct CORE_CLK_SEL_SPEC;
33impl crate::RegisterSpec for CORE_CLK_SEL_SPEC {
34    type Ux = u32;
35}
36#[doc = "`read()` method returns [`core_clk_sel::R`](R) reader structure"]
37impl crate::Readable for CORE_CLK_SEL_SPEC {}
38#[doc = "`write(|w| ..)` method takes [`core_clk_sel::W`](W) writer structure"]
39impl crate::Writable for CORE_CLK_SEL_SPEC {
40    type Safety = crate::Unsafe;
41    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
42    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
43}
44#[doc = "`reset()` method sets CORE_CLK_SEL to value 0"]
45impl crate::Resettable for CORE_CLK_SEL_SPEC {
46    const RESET_VALUE: u32 = 0;
47}
esp32c3/spi0/core_clk_sel.rs

esp32c3/spi0/
core_clk_sel.rs
