esp32c3/extmem/
core0_acs_cache_int_ena.rs

1#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` reader"]
2pub type R = crate::R<CORE0_ACS_CACHE_INT_ENA_SPEC>;
3#[doc = "Register `CORE0_ACS_CACHE_INT_ENA` writer"]
4pub type W = crate::W<CORE0_ACS_CACHE_INT_ENA_SPEC>;
5#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` reader - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
6pub type CORE0_IBUS_ACS_MSK_IC_R = crate::BitReader;
7#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` writer - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
8pub type CORE0_IBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE0_IBUS_WR_IC` reader - The bit is used to enable interrupt by ibus trying to write icache"]
10pub type CORE0_IBUS_WR_IC_R = crate::BitReader;
11#[doc = "Field `CORE0_IBUS_WR_IC` writer - The bit is used to enable interrupt by ibus trying to write icache"]
12pub type CORE0_IBUS_WR_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE0_IBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
14pub type CORE0_IBUS_REJECT_R = crate::BitReader;
15#[doc = "Field `CORE0_IBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
16pub type CORE0_IBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE0_DBUS_ACS_MSK_IC` reader - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access."]
18pub type CORE0_DBUS_ACS_MSK_IC_R = crate::BitReader;
19#[doc = "Field `CORE0_DBUS_ACS_MSK_IC` writer - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access."]
20pub type CORE0_DBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE0_DBUS_REJECT` reader - The bit is used to enable interrupt by authentication fail."]
22pub type CORE0_DBUS_REJECT_R = crate::BitReader;
23#[doc = "Field `CORE0_DBUS_REJECT` writer - The bit is used to enable interrupt by authentication fail."]
24pub type CORE0_DBUS_REJECT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CORE0_DBUS_WR_IC` reader - The bit is used to enable interrupt by dbus trying to write icache"]
26pub type CORE0_DBUS_WR_IC_R = crate::BitReader;
27#[doc = "Field `CORE0_DBUS_WR_IC` writer - The bit is used to enable interrupt by dbus trying to write icache"]
28pub type CORE0_DBUS_WR_IC_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
31    #[inline(always)]
32    pub fn core0_ibus_acs_msk_ic(&self) -> CORE0_IBUS_ACS_MSK_IC_R {
33        CORE0_IBUS_ACS_MSK_IC_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
36    #[inline(always)]
37    pub fn core0_ibus_wr_ic(&self) -> CORE0_IBUS_WR_IC_R {
38        CORE0_IBUS_WR_IC_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
41    #[inline(always)]
42    pub fn core0_ibus_reject(&self) -> CORE0_IBUS_REJECT_R {
43        CORE0_IBUS_REJECT_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access."]
46    #[inline(always)]
47    pub fn core0_dbus_acs_msk_ic(&self) -> CORE0_DBUS_ACS_MSK_IC_R {
48        CORE0_DBUS_ACS_MSK_IC_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
51    #[inline(always)]
52    pub fn core0_dbus_reject(&self) -> CORE0_DBUS_REJECT_R {
53        CORE0_DBUS_REJECT_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - The bit is used to enable interrupt by dbus trying to write icache"]
56    #[inline(always)]
57    pub fn core0_dbus_wr_ic(&self) -> CORE0_DBUS_WR_IC_R {
58        CORE0_DBUS_WR_IC_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("CORE0_ACS_CACHE_INT_ENA")
65            .field("core0_ibus_acs_msk_ic", &self.core0_ibus_acs_msk_ic())
66            .field("core0_ibus_wr_ic", &self.core0_ibus_wr_ic())
67            .field("core0_ibus_reject", &self.core0_ibus_reject())
68            .field("core0_dbus_acs_msk_ic", &self.core0_dbus_acs_msk_ic())
69            .field("core0_dbus_reject", &self.core0_dbus_reject())
70            .field("core0_dbus_wr_ic", &self.core0_dbus_wr_ic())
71            .finish()
72    }
73}
74impl W {
75    #[doc = "Bit 0 - The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access."]
76    #[inline(always)]
77    pub fn core0_ibus_acs_msk_ic(
78        &mut self,
79    ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
80        CORE0_IBUS_ACS_MSK_IC_W::new(self, 0)
81    }
82    #[doc = "Bit 1 - The bit is used to enable interrupt by ibus trying to write icache"]
83    #[inline(always)]
84    pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
85        CORE0_IBUS_WR_IC_W::new(self, 1)
86    }
87    #[doc = "Bit 2 - The bit is used to enable interrupt by authentication fail."]
88    #[inline(always)]
89    pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
90        CORE0_IBUS_REJECT_W::new(self, 2)
91    }
92    #[doc = "Bit 3 - The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access."]
93    #[inline(always)]
94    pub fn core0_dbus_acs_msk_ic(
95        &mut self,
96    ) -> CORE0_DBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
97        CORE0_DBUS_ACS_MSK_IC_W::new(self, 3)
98    }
99    #[doc = "Bit 4 - The bit is used to enable interrupt by authentication fail."]
100    #[inline(always)]
101    pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
102        CORE0_DBUS_REJECT_W::new(self, 4)
103    }
104    #[doc = "Bit 5 - The bit is used to enable interrupt by dbus trying to write icache"]
105    #[inline(always)]
106    pub fn core0_dbus_wr_ic(&mut self) -> CORE0_DBUS_WR_IC_W<CORE0_ACS_CACHE_INT_ENA_SPEC> {
107        CORE0_DBUS_WR_IC_W::new(self, 5)
108    }
109}
110#[doc = "This description will be updated in the near future.\n\nYou can [`read`](crate::Reg::read) this register and get [`core0_acs_cache_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
111pub struct CORE0_ACS_CACHE_INT_ENA_SPEC;
112impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_ENA_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [`core0_acs_cache_int_ena::R`](R) reader structure"]
116impl crate::Readable for CORE0_ACS_CACHE_INT_ENA_SPEC {}
117#[doc = "`write(|w| ..)` method takes [`core0_acs_cache_int_ena::W`](W) writer structure"]
118impl crate::Writable for CORE0_ACS_CACHE_INT_ENA_SPEC {
119    type Safety = crate::Unsafe;
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
122}
123#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_ENA to value 0"]
124impl crate::Resettable for CORE0_ACS_CACHE_INT_ENA_SPEC {
125    const RESET_VALUE: u32 = 0;
126}
esp32c3/extmem/core0_acs_cache_int_ena.rs

esp32c3/extmem/
core0_acs_cache_int_ena.rs
