esp32c3/extmem/
cache_acs_cnt_clr.rs

1#[doc = "Register `CACHE_ACS_CNT_CLR` writer"]
2pub type W = crate::W<CACHE_ACS_CNT_CLR_SPEC>;
3#[doc = "Field `IBUS_ACS_CNT_CLR` writer - The bit is used to clear ibus counter."]
4pub type IBUS_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `DBUS_ACS_CNT_CLR` writer - The bit is used to clear dbus counter."]
6pub type DBUS_ACS_CNT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[cfg(feature = "impl-register-debug")]
8impl core::fmt::Debug for crate::generic::Reg<CACHE_ACS_CNT_CLR_SPEC> {
9    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
10        write!(f, "(not readable)")
11    }
12}
13impl W {
14    #[doc = "Bit 0 - The bit is used to clear ibus counter."]
15    #[inline(always)]
16    pub fn ibus_acs_cnt_clr(&mut self) -> IBUS_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
17        IBUS_ACS_CNT_CLR_W::new(self, 0)
18    }
19    #[doc = "Bit 1 - The bit is used to clear dbus counter."]
20    #[inline(always)]
21    pub fn dbus_acs_cnt_clr(&mut self) -> DBUS_ACS_CNT_CLR_W<CACHE_ACS_CNT_CLR_SPEC> {
22        DBUS_ACS_CNT_CLR_W::new(self, 1)
23    }
24}
25#[doc = "This description will be updated in the near future.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cache_acs_cnt_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
26pub struct CACHE_ACS_CNT_CLR_SPEC;
27impl crate::RegisterSpec for CACHE_ACS_CNT_CLR_SPEC {
28    type Ux = u32;
29}
30#[doc = "`write(|w| ..)` method takes [`cache_acs_cnt_clr::W`](W) writer structure"]
31impl crate::Writable for CACHE_ACS_CNT_CLR_SPEC {
32    type Safety = crate::Unsafe;
33    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35}
36#[doc = "`reset()` method sets CACHE_ACS_CNT_CLR to value 0"]
37impl crate::Resettable for CACHE_ACS_CNT_CLR_SPEC {
38    const RESET_VALUE: u32 = 0;
39}
esp32c3/extmem/cache_acs_cnt_clr.rs

esp32c3/extmem/
cache_acs_cnt_clr.rs
