esp32c3/assist_debug/
core_0_intr_clr.rs

1#[doc = "Register `CORE_0_INTR_CLR` reader"]
2pub type R = crate::R<CORE_0_INTR_CLR_SPEC>;
3#[doc = "Register `CORE_0_INTR_CLR` writer"]
4pub type W = crate::W<CORE_0_INTR_CLR_SPEC>;
5#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_CLR` reader - reg_core_0_area_dram0_0_rd_clr"]
6pub type CORE_0_AREA_DRAM0_0_RD_CLR_R = crate::BitReader;
7#[doc = "Field `CORE_0_AREA_DRAM0_0_RD_CLR` writer - reg_core_0_area_dram0_0_rd_clr"]
8pub type CORE_0_AREA_DRAM0_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_CLR` reader - reg_core_0_area_dram0_0_wr_clr"]
10pub type CORE_0_AREA_DRAM0_0_WR_CLR_R = crate::BitReader;
11#[doc = "Field `CORE_0_AREA_DRAM0_0_WR_CLR` writer - reg_core_0_area_dram0_0_wr_clr"]
12pub type CORE_0_AREA_DRAM0_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_CLR` reader - reg_core_0_area_dram0_1_rd_clr"]
14pub type CORE_0_AREA_DRAM0_1_RD_CLR_R = crate::BitReader;
15#[doc = "Field `CORE_0_AREA_DRAM0_1_RD_CLR` writer - reg_core_0_area_dram0_1_rd_clr"]
16pub type CORE_0_AREA_DRAM0_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_CLR` reader - reg_core_0_area_dram0_1_wr_clr"]
18pub type CORE_0_AREA_DRAM0_1_WR_CLR_R = crate::BitReader;
19#[doc = "Field `CORE_0_AREA_DRAM0_1_WR_CLR` writer - reg_core_0_area_dram0_1_wr_clr"]
20pub type CORE_0_AREA_DRAM0_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CORE_0_AREA_PIF_0_RD_CLR` reader - reg_core_0_area_pif_0_rd_clr"]
22pub type CORE_0_AREA_PIF_0_RD_CLR_R = crate::BitReader;
23#[doc = "Field `CORE_0_AREA_PIF_0_RD_CLR` writer - reg_core_0_area_pif_0_rd_clr"]
24pub type CORE_0_AREA_PIF_0_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CORE_0_AREA_PIF_0_WR_CLR` reader - reg_core_0_area_pif_0_wr_clr"]
26pub type CORE_0_AREA_PIF_0_WR_CLR_R = crate::BitReader;
27#[doc = "Field `CORE_0_AREA_PIF_0_WR_CLR` writer - reg_core_0_area_pif_0_wr_clr"]
28pub type CORE_0_AREA_PIF_0_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CORE_0_AREA_PIF_1_RD_CLR` reader - reg_core_0_area_pif_1_rd_clr"]
30pub type CORE_0_AREA_PIF_1_RD_CLR_R = crate::BitReader;
31#[doc = "Field `CORE_0_AREA_PIF_1_RD_CLR` writer - reg_core_0_area_pif_1_rd_clr"]
32pub type CORE_0_AREA_PIF_1_RD_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CORE_0_AREA_PIF_1_WR_CLR` reader - reg_core_0_area_pif_1_wr_clr"]
34pub type CORE_0_AREA_PIF_1_WR_CLR_R = crate::BitReader;
35#[doc = "Field `CORE_0_AREA_PIF_1_WR_CLR` writer - reg_core_0_area_pif_1_wr_clr"]
36pub type CORE_0_AREA_PIF_1_WR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CORE_0_SP_SPILL_MIN_CLR` reader - reg_core_0_sp_spill_min_clr"]
38pub type CORE_0_SP_SPILL_MIN_CLR_R = crate::BitReader;
39#[doc = "Field `CORE_0_SP_SPILL_MIN_CLR` writer - reg_core_0_sp_spill_min_clr"]
40pub type CORE_0_SP_SPILL_MIN_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CORE_0_SP_SPILL_MAX_CLR` reader - reg_core_0_sp_spill_max_clr"]
42pub type CORE_0_SP_SPILL_MAX_CLR_R = crate::BitReader;
43#[doc = "Field `CORE_0_SP_SPILL_MAX_CLR` writer - reg_core_0_sp_spill_max_clr"]
44pub type CORE_0_SP_SPILL_MAX_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_CLR` reader - reg_core_0_iram0_exception_monitor_clr"]
46pub type CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
47#[doc = "Field `CORE_0_IRAM0_EXCEPTION_MONITOR_CLR` writer - reg_core_0_iram0_exception_monitor_clr"]
48pub type CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_CLR` reader - reg_core_0_dram0_exception_monitor_clr"]
50pub type CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R = crate::BitReader;
51#[doc = "Field `CORE_0_DRAM0_EXCEPTION_MONITOR_CLR` writer - reg_core_0_dram0_exception_monitor_clr"]
52pub type CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54    #[doc = "Bit 0 - reg_core_0_area_dram0_0_rd_clr"]
55    #[inline(always)]
56    pub fn core_0_area_dram0_0_rd_clr(&self) -> CORE_0_AREA_DRAM0_0_RD_CLR_R {
57        CORE_0_AREA_DRAM0_0_RD_CLR_R::new((self.bits & 1) != 0)
58    }
59    #[doc = "Bit 1 - reg_core_0_area_dram0_0_wr_clr"]
60    #[inline(always)]
61    pub fn core_0_area_dram0_0_wr_clr(&self) -> CORE_0_AREA_DRAM0_0_WR_CLR_R {
62        CORE_0_AREA_DRAM0_0_WR_CLR_R::new(((self.bits >> 1) & 1) != 0)
63    }
64    #[doc = "Bit 2 - reg_core_0_area_dram0_1_rd_clr"]
65    #[inline(always)]
66    pub fn core_0_area_dram0_1_rd_clr(&self) -> CORE_0_AREA_DRAM0_1_RD_CLR_R {
67        CORE_0_AREA_DRAM0_1_RD_CLR_R::new(((self.bits >> 2) & 1) != 0)
68    }
69    #[doc = "Bit 3 - reg_core_0_area_dram0_1_wr_clr"]
70    #[inline(always)]
71    pub fn core_0_area_dram0_1_wr_clr(&self) -> CORE_0_AREA_DRAM0_1_WR_CLR_R {
72        CORE_0_AREA_DRAM0_1_WR_CLR_R::new(((self.bits >> 3) & 1) != 0)
73    }
74    #[doc = "Bit 4 - reg_core_0_area_pif_0_rd_clr"]
75    #[inline(always)]
76    pub fn core_0_area_pif_0_rd_clr(&self) -> CORE_0_AREA_PIF_0_RD_CLR_R {
77        CORE_0_AREA_PIF_0_RD_CLR_R::new(((self.bits >> 4) & 1) != 0)
78    }
79    #[doc = "Bit 5 - reg_core_0_area_pif_0_wr_clr"]
80    #[inline(always)]
81    pub fn core_0_area_pif_0_wr_clr(&self) -> CORE_0_AREA_PIF_0_WR_CLR_R {
82        CORE_0_AREA_PIF_0_WR_CLR_R::new(((self.bits >> 5) & 1) != 0)
83    }
84    #[doc = "Bit 6 - reg_core_0_area_pif_1_rd_clr"]
85    #[inline(always)]
86    pub fn core_0_area_pif_1_rd_clr(&self) -> CORE_0_AREA_PIF_1_RD_CLR_R {
87        CORE_0_AREA_PIF_1_RD_CLR_R::new(((self.bits >> 6) & 1) != 0)
88    }
89    #[doc = "Bit 7 - reg_core_0_area_pif_1_wr_clr"]
90    #[inline(always)]
91    pub fn core_0_area_pif_1_wr_clr(&self) -> CORE_0_AREA_PIF_1_WR_CLR_R {
92        CORE_0_AREA_PIF_1_WR_CLR_R::new(((self.bits >> 7) & 1) != 0)
93    }
94    #[doc = "Bit 8 - reg_core_0_sp_spill_min_clr"]
95    #[inline(always)]
96    pub fn core_0_sp_spill_min_clr(&self) -> CORE_0_SP_SPILL_MIN_CLR_R {
97        CORE_0_SP_SPILL_MIN_CLR_R::new(((self.bits >> 8) & 1) != 0)
98    }
99    #[doc = "Bit 9 - reg_core_0_sp_spill_max_clr"]
100    #[inline(always)]
101    pub fn core_0_sp_spill_max_clr(&self) -> CORE_0_SP_SPILL_MAX_CLR_R {
102        CORE_0_SP_SPILL_MAX_CLR_R::new(((self.bits >> 9) & 1) != 0)
103    }
104    #[doc = "Bit 10 - reg_core_0_iram0_exception_monitor_clr"]
105    #[inline(always)]
106    pub fn core_0_iram0_exception_monitor_clr(&self) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R {
107        CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 10) & 1) != 0)
108    }
109    #[doc = "Bit 11 - reg_core_0_dram0_exception_monitor_clr"]
110    #[inline(always)]
111    pub fn core_0_dram0_exception_monitor_clr(&self) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R {
112        CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_R::new(((self.bits >> 11) & 1) != 0)
113    }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118        f.debug_struct("CORE_0_INTR_CLR")
119            .field(
120                "core_0_area_dram0_0_rd_clr",
121                &self.core_0_area_dram0_0_rd_clr(),
122            )
123            .field(
124                "core_0_area_dram0_0_wr_clr",
125                &self.core_0_area_dram0_0_wr_clr(),
126            )
127            .field(
128                "core_0_area_dram0_1_rd_clr",
129                &self.core_0_area_dram0_1_rd_clr(),
130            )
131            .field(
132                "core_0_area_dram0_1_wr_clr",
133                &self.core_0_area_dram0_1_wr_clr(),
134            )
135            .field("core_0_area_pif_0_rd_clr", &self.core_0_area_pif_0_rd_clr())
136            .field("core_0_area_pif_0_wr_clr", &self.core_0_area_pif_0_wr_clr())
137            .field("core_0_area_pif_1_rd_clr", &self.core_0_area_pif_1_rd_clr())
138            .field("core_0_area_pif_1_wr_clr", &self.core_0_area_pif_1_wr_clr())
139            .field("core_0_sp_spill_min_clr", &self.core_0_sp_spill_min_clr())
140            .field("core_0_sp_spill_max_clr", &self.core_0_sp_spill_max_clr())
141            .field(
142                "core_0_iram0_exception_monitor_clr",
143                &self.core_0_iram0_exception_monitor_clr(),
144            )
145            .field(
146                "core_0_dram0_exception_monitor_clr",
147                &self.core_0_dram0_exception_monitor_clr(),
148            )
149            .finish()
150    }
151}
152impl W {
153    #[doc = "Bit 0 - reg_core_0_area_dram0_0_rd_clr"]
154    #[inline(always)]
155    pub fn core_0_area_dram0_0_rd_clr(
156        &mut self,
157    ) -> CORE_0_AREA_DRAM0_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
158        CORE_0_AREA_DRAM0_0_RD_CLR_W::new(self, 0)
159    }
160    #[doc = "Bit 1 - reg_core_0_area_dram0_0_wr_clr"]
161    #[inline(always)]
162    pub fn core_0_area_dram0_0_wr_clr(
163        &mut self,
164    ) -> CORE_0_AREA_DRAM0_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
165        CORE_0_AREA_DRAM0_0_WR_CLR_W::new(self, 1)
166    }
167    #[doc = "Bit 2 - reg_core_0_area_dram0_1_rd_clr"]
168    #[inline(always)]
169    pub fn core_0_area_dram0_1_rd_clr(
170        &mut self,
171    ) -> CORE_0_AREA_DRAM0_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
172        CORE_0_AREA_DRAM0_1_RD_CLR_W::new(self, 2)
173    }
174    #[doc = "Bit 3 - reg_core_0_area_dram0_1_wr_clr"]
175    #[inline(always)]
176    pub fn core_0_area_dram0_1_wr_clr(
177        &mut self,
178    ) -> CORE_0_AREA_DRAM0_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
179        CORE_0_AREA_DRAM0_1_WR_CLR_W::new(self, 3)
180    }
181    #[doc = "Bit 4 - reg_core_0_area_pif_0_rd_clr"]
182    #[inline(always)]
183    pub fn core_0_area_pif_0_rd_clr(&mut self) -> CORE_0_AREA_PIF_0_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
184        CORE_0_AREA_PIF_0_RD_CLR_W::new(self, 4)
185    }
186    #[doc = "Bit 5 - reg_core_0_area_pif_0_wr_clr"]
187    #[inline(always)]
188    pub fn core_0_area_pif_0_wr_clr(&mut self) -> CORE_0_AREA_PIF_0_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
189        CORE_0_AREA_PIF_0_WR_CLR_W::new(self, 5)
190    }
191    #[doc = "Bit 6 - reg_core_0_area_pif_1_rd_clr"]
192    #[inline(always)]
193    pub fn core_0_area_pif_1_rd_clr(&mut self) -> CORE_0_AREA_PIF_1_RD_CLR_W<CORE_0_INTR_CLR_SPEC> {
194        CORE_0_AREA_PIF_1_RD_CLR_W::new(self, 6)
195    }
196    #[doc = "Bit 7 - reg_core_0_area_pif_1_wr_clr"]
197    #[inline(always)]
198    pub fn core_0_area_pif_1_wr_clr(&mut self) -> CORE_0_AREA_PIF_1_WR_CLR_W<CORE_0_INTR_CLR_SPEC> {
199        CORE_0_AREA_PIF_1_WR_CLR_W::new(self, 7)
200    }
201    #[doc = "Bit 8 - reg_core_0_sp_spill_min_clr"]
202    #[inline(always)]
203    pub fn core_0_sp_spill_min_clr(&mut self) -> CORE_0_SP_SPILL_MIN_CLR_W<CORE_0_INTR_CLR_SPEC> {
204        CORE_0_SP_SPILL_MIN_CLR_W::new(self, 8)
205    }
206    #[doc = "Bit 9 - reg_core_0_sp_spill_max_clr"]
207    #[inline(always)]
208    pub fn core_0_sp_spill_max_clr(&mut self) -> CORE_0_SP_SPILL_MAX_CLR_W<CORE_0_INTR_CLR_SPEC> {
209        CORE_0_SP_SPILL_MAX_CLR_W::new(self, 9)
210    }
211    #[doc = "Bit 10 - reg_core_0_iram0_exception_monitor_clr"]
212    #[inline(always)]
213    pub fn core_0_iram0_exception_monitor_clr(
214        &mut self,
215    ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
216        CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 10)
217    }
218    #[doc = "Bit 11 - reg_core_0_dram0_exception_monitor_clr"]
219    #[inline(always)]
220    pub fn core_0_dram0_exception_monitor_clr(
221        &mut self,
222    ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W<CORE_0_INTR_CLR_SPEC> {
223        CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W::new(self, 11)
224    }
225}
226#[doc = "ASSIST_DEBUG_CORE_0_INTR_CLR_REG\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_intr_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_intr_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct CORE_0_INTR_CLR_SPEC;
228impl crate::RegisterSpec for CORE_0_INTR_CLR_SPEC {
229    type Ux = u32;
230}
231#[doc = "`read()` method returns [`core_0_intr_clr::R`](R) reader structure"]
232impl crate::Readable for CORE_0_INTR_CLR_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`core_0_intr_clr::W`](W) writer structure"]
234impl crate::Writable for CORE_0_INTR_CLR_SPEC {
235    type Safety = crate::Unsafe;
236    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
237    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
238}
239#[doc = "`reset()` method sets CORE_0_INTR_CLR to value 0"]
240impl crate::Resettable for CORE_0_INTR_CLR_SPEC {
241    const RESET_VALUE: u32 = 0;
242}
esp32c3/assist_debug/core_0_intr_clr.rs

esp32c3/assist_debug/
core_0_intr_clr.rs
