Expand description
SPI1 control register.
Structs§
- SPI1 control register.
Type Aliases§
- Field
D_POL
reader - The bit is used to set MOSI line polarity, 1: high 0, low - Field
D_POL
writer - The bit is used to set MOSI line polarity, 1: high 0, low - Field
FASTRD_MODE
reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. - Field
FASTRD_MODE
writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable. - Field
FCMD_DUAL
reader - Apply 2 signals during command phase 1:enable 0: disable - Field
FCMD_DUAL
writer - Apply 2 signals during command phase 1:enable 0: disable - Field
FCMD_QUAD
reader - Apply 4 signals during command phase 1:enable 0: disable - Field
FCMD_QUAD
writer - Apply 4 signals during command phase 1:enable 0: disable - Field
FCS_CRC_EN
reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. - Field
FCS_CRC_EN
writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low. - Field
FDUMMY_OUT
reader - In the dummy phase the signal level of spi is output by the spi controller. - Field
FDUMMY_OUT
writer - In the dummy phase the signal level of spi is output by the spi controller. - Field
FREAD_DIO
reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. - Field
FREAD_DIO
writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable. - Field
FREAD_DUAL
reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - Field
FREAD_DUAL
writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - Field
FREAD_QIO
reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. - Field
FREAD_QIO
writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable. - Field
FREAD_QUAD
reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - Field
FREAD_QUAD
writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - Field
Q_POL
reader - The bit is used to set MISO line polarity, 1: high 0, low - Field
Q_POL
writer - The bit is used to set MISO line polarity, 1: high 0, low - Register
CTRL
reader - Field
RESANDRES
reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. - Field
RESANDRES
writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. - Field
TX_CRC_EN
reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable - Field
TX_CRC_EN
writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable - Register
CTRL
writer - Field
WP
reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. - Field
WP
writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. - Field
WRSR_2B
reader - two bytes data will be written to status register when it is set. 1: enable 0: disable. - Field
WRSR_2B
writer - two bytes data will be written to status register when it is set. 1: enable 0: disable.