Type Alias esp32c3::assist_debug::core_0_intr_ena::W

pub type W = W<CORE_0_INTR_ENA_SPEC>;

Register CORE_0_INTR_ENA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn core_0_area_dram0_0_rd_intr_ena( &mut self ) -> CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 0 - reg_core_0_area_dram0_0_rd_intr_ena

pub fn core_0_area_dram0_0_wr_intr_ena( &mut self ) -> CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 1 - reg_core_0_area_dram0_0_wr_intr_ena

pub fn core_0_area_dram0_1_rd_intr_ena( &mut self ) -> CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 2 - reg_core_0_area_dram0_1_rd_intr_ena

pub fn core_0_area_dram0_1_wr_intr_ena( &mut self ) -> CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 3 - reg_core_0_area_dram0_1_wr_intr_ena

pub fn core_0_area_pif_0_rd_intr_ena( &mut self ) -> CORE_0_AREA_PIF_0_RD_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 4 - reg_core_0_area_pif_0_rd_intr_ena

pub fn core_0_area_pif_0_wr_intr_ena( &mut self ) -> CORE_0_AREA_PIF_0_WR_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 5 - reg_core_0_area_pif_0_wr_intr_ena

pub fn core_0_area_pif_1_rd_intr_ena( &mut self ) -> CORE_0_AREA_PIF_1_RD_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 6 - reg_core_0_area_pif_1_rd_intr_ena

pub fn core_0_area_pif_1_wr_intr_ena( &mut self ) -> CORE_0_AREA_PIF_1_WR_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 7 - reg_core_0_area_pif_1_wr_intr_ena

pub fn core_0_sp_spill_min_intr_ena( &mut self ) -> CORE_0_SP_SPILL_MIN_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 8 - reg_core_0_sp_spill_min_intr_ena

pub fn core_0_sp_spill_max_intr_ena( &mut self ) -> CORE_0_SP_SPILL_MAX_INTR_ENA_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 9 - reg_core_0_sp_spill_max_intr_ena

pub fn core_0_iram0_exception_monitor_rls( &mut self ) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 10 - reg_core_0_iram0_exception_monitor_ena

pub fn core_0_dram0_exception_monitor_rls( &mut self ) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W<'_, CORE_0_INTR_ENA_SPEC>

Bit 11 - reg_core_0_dram0_exception_monitor_ena