Module esp32c3::uart0

UART (Universal Asynchronous Receiver-Transmitter) Controller 0

Modules

• at_cmd_char
  AT escape sequence detection configuration
• at_cmd_gaptout
  Timeout configuration
• at_cmd_postcnt
  Post-sequence timing configuration
• at_cmd_precnt
  Pre-sequence timing configuration
• clk_conf
  UART core clock configuration
• clkdiv
  Clock divider configuration
• conf0
  a
• conf1
  Configuration register 1
• date
  UART Version register
• fifo
  FIFO data register
• flow_conf
  Software flow-control configuration
• fsm_status
  UART transmit and receive status.
• highpulse
  Autobaud minimum high pulse duration register
• id
  UART ID register
• idle_conf
  Frame-end idle configuration
• int_clr
  Interrupt clear bits
• int_ena
  Interrupt enable bits
• int_raw
  Raw interrupt status
• int_st
  Masked interrupt status
• lowpulse
  Autobaud minimum low pulse duration register
• mem_conf
  UART threshold and allocation configuration
• mem_rx_status
  Rx-FIFO write and read offset address.
• mem_tx_status
  Tx-FIFO write and read offset address.
• negpulse
  Autobaud low pulse register
• pospulse
  Autobaud high pulse register
• rs485_conf
  RS485 mode configuration
• rx_filt
  Rx Filter configuration
• rxd_cnt
  Autobaud edge change count register
• sleep_conf
  Sleep-mode configuration
• status
  UART status register
• swfc_conf0
  Software flow-control character configuration
• swfc_conf1
  Software flow-control character configuration
• txbrk_conf
  Tx Break character configuration

Structs

• RegisterBlock
  Register block

Type Aliases

• AT_CMD_CHAR
  AT_CMD_CHAR (rw) register accessor: AT escape sequence detection configuration
• AT_CMD_GAPTOUT
  AT_CMD_GAPTOUT (rw) register accessor: Timeout configuration
• AT_CMD_POSTCNT
  AT_CMD_POSTCNT (rw) register accessor: Post-sequence timing configuration
• AT_CMD_PRECNT
  AT_CMD_PRECNT (rw) register accessor: Pre-sequence timing configuration
• CLKDIV
  CLKDIV (rw) register accessor: Clock divider configuration
• CLK_CONF
  CLK_CONF (rw) register accessor: UART core clock configuration
• CONF0
  CONF0 (rw) register accessor: a
• CONF1
  CONF1 (rw) register accessor: Configuration register 1
• DATE
  DATE (rw) register accessor: UART Version register
• FIFO
  FIFO (rw) register accessor: FIFO data register
• FLOW_CONF
  FLOW_CONF (rw) register accessor: Software flow-control configuration
• FSM_STATUS
  FSM_STATUS (r) register accessor: UART transmit and receive status.
• HIGHPULSE
  HIGHPULSE (r) register accessor: Autobaud minimum high pulse duration register
• ID
  ID (rw) register accessor: UART ID register
• IDLE_CONF
  IDLE_CONF (rw) register accessor: Frame-end idle configuration
• INT_CLR
  INT_CLR (w) register accessor: Interrupt clear bits
• INT_ENA
  INT_ENA (rw) register accessor: Interrupt enable bits
• INT_RAW
  INT_RAW (rw) register accessor: Raw interrupt status
• INT_ST
  INT_ST (r) register accessor: Masked interrupt status
• LOWPULSE
  LOWPULSE (r) register accessor: Autobaud minimum low pulse duration register
• MEM_CONF
  MEM_CONF (rw) register accessor: UART threshold and allocation configuration
• MEM_RX_STATUS
  MEM_RX_STATUS (r) register accessor: Rx-FIFO write and read offset address.
• MEM_TX_STATUS
  MEM_TX_STATUS (r) register accessor: Tx-FIFO write and read offset address.
• NEGPULSE
  NEGPULSE (r) register accessor: Autobaud low pulse register
• POSPULSE
  POSPULSE (r) register accessor: Autobaud high pulse register
• RS485_CONF
  RS485_CONF (rw) register accessor: RS485 mode configuration
• RXD_CNT
  RXD_CNT (r) register accessor: Autobaud edge change count register
• RX_FILT
  RX_FILT (rw) register accessor: Rx Filter configuration
• SLEEP_CONF
  SLEEP_CONF (rw) register accessor: Sleep-mode configuration
• STATUS
  STATUS (r) register accessor: UART status register
• SWFC_CONF0
  SWFC_CONF0 (rw) register accessor: Software flow-control character configuration
• SWFC_CONF1
  SWFC_CONF1 (rw) register accessor: Software flow-control character configuration
• TXBRK_CONF
  TXBRK_CONF (rw) register accessor: Tx Break character configuration